The Tool Desk
Outbyte PC Repair FREEClear out junk files and repair common Windows errorsFree Scan →Outbyte Driver Updater FREEScan for outdated or missing drivers - takes under a minuteDriver Scan →No—an SSD cannot replace DRAM or GPU HBM as the active working memory for AI computation. It can, however, add a much larger and cheaper capacity tier. With software that deliberately offloads model weights, datasets, or inference KV-cache data, NVMe storage lets a system run workloads that do not fit entirely in GPU memory or host DRAM. The cost is transfer latency, lower effective bandwidth, software complexity, and possible SSD wear.
What “replace DRAM” would mean
DRAM and GPU high-bandwidth memory (HBM) hold the data processors are actively reading and writing. An SSD is non-volatile storage: data remains on it when power is removed, but the processor must move that data through an I/O path before computation can use it. That distinction determines the answer.
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When an AI kernel repeatedly needs data that resides on an SSD, each miss becomes a storage request, a transfer across the host and PCIe path, and often a copy into CPU or GPU memory. The compute units may wait while that movement occurs. NVIDIA’s storage guidance describes the consequence directly: when a GPU traverses the data fabric to internal or external storage for part of a model or dataset, swapping to disk substantially reduces training performance.
Therefore, an SSD is best viewed as a capacity-extension tier, not a memory substitute. It can prevent an out-of-memory failure or make a larger model serviceable, but it does not offer the latency or bandwidth characteristics required to act like local DRAM or HBM.
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Where each tier fits in an AI system
| Tier | Primary role | What happens when capacity is insufficient | Important qualification |
|---|---|---|---|
| GPU HBM | Active model weights, activations, and working state closest to GPU execution | Data must be staged from another tier, or the workload must be reduced or partitioned | Capacity is fixed by the GPU configuration; moving data out adds transfer overhead |
| Host DRAM | CPU-side working memory and a larger, slower tier than GPU memory | Data may be copied to GPU memory in batches or managed by a tiering system | It remains memory, not NVMe block storage; no universal DRAM-to-HBM ratio applies to every platform |
| CXL memory | Memory expansion or pooling over the Compute Express Link interconnect | Hardware- or software-managed placement can keep hot pages nearer to the CPU | Microsoft Research reports higher latency than local DRAM, with results strongly affected by contention and access pattern |
| NVMe SSD | Durable, high-capacity storage for datasets, checkpoints, model weights, and selected offload data | Software fetches blocks into DRAM or HBM when needed | Capacity is scalable, but access is far slower than memory and consumes I/O bandwidth |
NVMe is an industry-standard interface for PCIe-attached SSDs across several form factors. NVM Express says version 2.4 was released on August 4, 2026, after Base Specification Revision 2.4 was ratified on July 31, 2026. That specification defines the interface; it does not make every NVMe drive suitable for sustained AI offload.
Useful AI workloads for SSD offload
Model weights that do not fit in HBM
Inference software can keep a model’s less frequently used weights on host storage and stage portions into GPU memory. This enables a larger model than the GPU could hold alone, but the execution plan must limit how often those portions are fetched. Layer-by-layer or expert-by-expert movement can work when transfers are predictable and overlapped with computation. Randomly requesting many small weight fragments during a kernel usually performs poorly.
Large training and fine-tuning datasets
An SSD is a practical source for training data, sharded datasets, checkpoints, and preprocessing caches. The normal pattern is to stream batches into host memory and then to the accelerator. Here the SSD is supplying a pipeline, not replacing DRAM: adequate read-ahead and buffering keep the GPU supplied while the next batch is read.
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Long-context and multi-user inference can make the key-value cache larger than available HBM. Frameworks can evict colder cache blocks to NVMe and retrieve them when a sequence resumes. IBM Research analyzed DeepSpeed and FlexGen traces for this type of model-weight and KV-cache offload. Its findings demonstrate a capacity use case, not equivalence between SSD and memory.
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How an SSD offload path works
- Choose the data to tier. Identify weights, cache blocks, or dataset shards that are too large for HBM and DRAM but are not needed on every compute step.
- Use framework support rather than ad hoc file reads. Offload-aware runtimes track residency, issue asynchronous I/O, and coordinate copies into CPU and GPU buffers. Without that coordination, synchronous reads can stall kernels.
- Reserve staging buffers. Allocate host memory for read-ahead, pinned transfers where supported, and enough queue depth to keep the storage device busy without starving the application.
- Schedule transfers ahead of demand. Prefetch predictable layers or cache blocks while current work is executing. Evict cold data only after confirming that its next use is not imminent.
- Measure the complete path. Record storage latency, queue depth, PCIe utilization, host-to-device copy time, GPU idle time, and application throughput. Drive-level sequential bandwidth alone is not an AI performance result.
- Set a fallback policy. If a cache miss would cause unacceptable latency, retain a larger hot set in DRAM or HBM, reduce context length, lower concurrency, or reject work rather than allowing uncontrolled swapping.
What published measurements actually show
| Source and setup | Reported result | How to interpret it |
|---|---|---|
| IBM Research, 2025; DeepSpeed and FlexGen LLM offload traces | Average read bandwidth of 2.0 GiB/s and average write bandwidth of 11.0 MiB/s; 128 KiB requests dominated the block-layer workload | Characterizes the studied KV-cache traces. It is not a guaranteed result for every SSD, framework, or workload. |
| Microsoft Research, Intel Flat Memory Mode prototype with hardware-managed CXL tiering | More than 82% of workloads had no more than 5% performance degradation; outliers reached 34% degradation | Results belong to that prototype and workload set. Contention and conflicting access patterns caused the largest losses. |
| Samsung Semiconductor evaluation; NVIDIA RTX PRO 6000 Blackwell GPUs, 1 TB CXL pool, vLLM, and LMCache | Examined inference KV-cache offload and compared the capacity problem across storage and memory tiers | Samsung says SSD and network-attached-memory offload can add latency and bandwidth overhead. The page does not establish an independent, universal benchmark. |
| September 20, 2026 arXiv preprint on CXL-SSD | The stock CXL-SSD in the tested setup was about three times slower than local DRAM and no faster than an NVMe SSD | A setup-specific result. The proposed chunk-aware method is not a commercial-product recommendation. |
IBM’s statement that “model offloading does not saturate NVMe SSDs” applies narrowly to the DeepSpeed and FlexGen traces it characterized. A low observed device-utilization rate can mean that software, request size, synchronization, or transfer staging—not NAND media bandwidth—is the bottleneck.
Access pattern matters more than the SSD label
Streaming and sequential reads
Large, predictable reads are the most favorable pattern. Dataset pipelines and planned layer prefetches can amortize command and transfer overhead, especially when several requests are overlapped.
Repeated hot-set access
If the same weights or cache blocks are repeatedly needed, keeping them in HBM or DRAM is usually better than reading them from storage each time. An SSD can hold the cold portion while a bounded hot set remains resident.
Random or latency-sensitive access
Small, unpredictable requests expose storage latency and software overhead. They can also create contention with checkpointing, logging, or other tenants. Larger request aggregation, locality-aware placement, and admission policies can reduce—but not eliminate—the penalty.
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Write-heavy cache policies
Evicting and rewriting KV-cache blocks increases write amplification and endurance consumption. IBM’s trace had far more read than write bandwidth, but that ratio belongs to its tested workload; a different eviction policy or persistence requirement can reverse the balance.
SSD versus CXL memory expansion
CXL memory sits between local DRAM and storage in the design space, but it is not automatically equivalent to either. It extends memory capacity through an interconnect and can support hardware-managed or software-managed placement. Microsoft Research found that CXL accesses have higher latency than local DRAM, while many workloads in its prototype stayed close to regular-DRAM performance and outliers suffered substantial degradation.
Samsung’s inference evaluation uses a 1 TB CXL memory pool with vLLM and LMCache to examine KV-cache capacity. This approach can keep data in a memory-oriented tier instead of a block-storage path, but it requires compatible CPUs, fabric, firmware, software, and memory devices. The September 2026 CXL-SSD preprint further illustrates why the name “CXL” is not enough to predict performance: its tested CXL-SSD was roughly three times slower than local DRAM and no faster than NVMe.
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Evaluation checklist for an AI server
- Capacity: quantify the model, dataset, checkpoint, and KV-cache footprint beyond available HBM and DRAM.
- Working-set fraction: estimate how much data must be fetched during each token, batch, or training step.
- Latency and bandwidth: measure end-to-end transfer time, not the SSD’s peak specification.
- Access pattern: classify requests as sequential, repeated, random, read-heavy, or write-heavy; include request-size distributions.
- Software path: verify that the chosen framework supports asynchronous offload, prefetch, eviction, and recovery from I/O errors.
- Interconnect compatibility: check PCIe generation and lane allocation, CPU and GPU topology, NUMA placement, thermals, and CXL support where applicable.
- Endurance: calculate expected bytes written from cache churn, checkpoints, and logs against the drive’s endurance rating.
- Isolation: determine whether training, inference, checkpointing, and operating-system activity share the same device.
- Total cost: include SSDs, DRAM, HBM-equipped accelerators, host CPUs, PCIe switches, cooling, power, and engineering time.
Common failure modes and fixes
“The model loads, but tokens per second collapse”
The active set is likely being fetched repeatedly. Increase the resident hot set, reduce concurrency or context length, shard the model to reduce movement, and add asynchronous prefetch. Confirm improvement by checking GPU idle intervals and host-to-device copy time.
“Peak SSD bandwidth looks high, but training is slow”
Peak sequential figures do not describe small or synchronized requests. Inspect request sizes, queue depth, read amplification, CPU copies, and PCIe contention. IBM’s 128 KiB request observation is a reminder to profile the actual block workload.
“Offload causes latency spikes under load”
Multiple users may be competing for the same queue or PCIe path. Reserve capacity for the hot path, cap queue depth, separate checkpoint traffic, and use admission control when the cache cannot be served within the latency target.
“The SSD wears out quickly”
Measure bytes written and write amplification rather than assuming a read-dominant workload. Reduce unnecessary persistence, batch writes, avoid rewriting unchanged cache blocks, and select an endurance rating appropriate for the measured workload.
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“CXL performed differently than expected”
Check the exact CXL device, firmware, memory mode, NUMA placement, and contention pattern. Published CXL results are tied to specific prototypes and workloads; they are not interchangeable product guarantees.
When an SSD-backed design is sensible
- The goal is to run a model or cache that exceeds HBM or DRAM capacity, and some extra latency is acceptable.
- Data movement is predictable enough to prefetch or batch.
- The framework has tested offload support and a clear fallback when storage is slow.
- The system has sufficient PCIe bandwidth, host memory, cooling, and endurance for sustained operation.
- Capacity and total-system cost matter more than matching in-memory performance.
It is a poor fit when every token requires random storage reads, when training throughput is the primary objective, or when the service has strict tail-latency requirements that cannot tolerate cache misses. In those cases, add HBM or DRAM, use a suitable CXL memory tier, reduce the working set, or redesign the model and serving policy before relying on SSD swapping.
Bottom line
SSDs expand AI capacity; they do not replace DRAM. Use NVMe as a deliberate offload and storage tier for cold model weights, datasets, checkpoints, and selected KV-cache blocks. Keep actively reused data in HBM or DRAM, measure the full transfer path, and select CXL or additional memory when the workload needs memory-like access rather than merely more capacity.
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