Yes, a 1 nm semiconductor technology generation is a plausible long-range research target, but no source cited here establishes that a commercial 1 nm process is in production or gives a firm date for one. The name would identify a process generation; it would not mean every transistor feature measures 1 nm. Imec describes a possible path toward such a node, built from proposed changes to transistors, materials, contacts and wiring—not a finished manufacturing process.
What does “1 nm” mean?
In semiconductor roadmaps, a node name such as “1 nm” is a technology-generation label. It is not a reliable measurement of every feature on a chip. To understand a specific claim, check which physical quantity it names:
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- Gate length is the length of the transistor channel controlled by its gate.
- Gate pitch is the repeated spacing between gates in a layout.
- Metal pitch describes spacing in a wiring layer.
- Node or process-generation name identifies a generation, not necessarily any one of those dimensions.
These measurements describe different things and cannot be substituted for one another. TSMC’s 2019 explainer used a typical gate length of about 20 nm as an example of transistor scale at that time; it is a historical example, not a universal present-day specification. TSMC also characterizes Moore’s Law as a guideline based on historical observation and future prediction, rather than a physical law that guarantees a particular schedule.
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Imec’s roadmap treats continued scaling as a coordinated effort across the front end of the manufacturing process, the middle of the line and the back end. Shrinking or changing the transistor alone is not enough: a denser layout also makes it harder to connect each device’s source, drain and gate to the wider network of chip wiring.
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Transistor architectures
The roadmap describes a progression from FinFETs to gate-all-around (GAA) nanosheet transistors, followed by possible forksheet devices and complementary FETs (CFETs). A CFET stacks n-type and p-type transistors vertically, potentially using chip area more efficiently. These are candidate steps in a scaling roadmap, not a settled list of devices that every manufacturer will use.
Materials and channels
Imec identifies two-dimensional channel materials and atomic channels as research directions for the 1 nm generation and beyond. Intel has also reported research on 2D transition-metal dichalcogenide transistors aimed at physical gate lengths below 10 nm. That research direction does not establish a commercial 1 nm process or show that a complete chip can be manufactured at that generation.
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Contacts, wiring and patterning
More compact devices need contacts and local interconnects that can still be manufactured and integrated reliably. Imec’s roadmap therefore includes possible changes to contacts, interconnects and back-end materials, alongside continued work on extreme ultraviolet (EUV) and high-NA EUV patterning. Yield, reliability, lithography and manufacturing cost all matter alongside device dimensions; success in one area by itself would not make a production process viable.
What the reported numbers do—and do not—show
The figures below refer to different metrics and kinds of announcements. None is a measurement of a commercial 1 nm node.
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| Figure | What it measures | What the source establishes |
|---|---|---|
| About 20 nm | Typical transistor gate length | TSMC’s 2019 explainer gives this as a historical example of transistor scale at that time, not a current universal specification. |
| 60 nm | Gate pitch | Intel reported vertically stacked CFET research at IEDM 2023 with gate pitch down to 60 nm. This is a research result, not evidence of a production 1 nm process. |
| 45 nm | Gate pitch | Intel’s June 2026 announcement describes monolithic CFET inverter research presented at the 2026 VLSI Symposium. It presents the work as a long-term path beyond GAA transistors, not as a 1 nm node. |
| 6% area savings | Area relative to A14 | In April 2026, TSMC said its A13 process would provide 6% area savings from A14 and was scheduled for production in 2029. TSMC described A13 as using nanosheet transistors; it did not identify A13 as a 1 nm node. |
In particular, gate pitch and gate length are not interchangeable, and neither is equivalent to a node label. Intel’s CFET pitch figures show reported research progress on a particular layout measurement; they do not mean the transistors have a 1 nm gate length or that the work is a 1 nm production process.
Is 1 nm already in production, or scheduled?
No commercial 1 nm process in production is established by the cited sources. Imec calls its proposals a possible path toward the 1 nm technology node. That wording describes a roadmap, not a manufacturing announcement.
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The cited company announcements also do not establish a 1 nm production date. Intel’s 2023 and 2026 CFET results are research reports. TSMC’s A13 announcement concerns a different named generation, with production scheduled for 2029; it is not a declaration of a 1 nm process. The sources provide no named, attributable statistic that establishes when a commercial 1 nm process will reach high-volume production, so dates for other nodes or research milestones should not be treated as a forecast for one.
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When a company or roadmap uses the term, these questions help distinguish a label from a demonstrated manufacturing capability:
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- Is 1 nm a node name or a physical dimension? Look for a defined gate length, gate pitch or metal pitch, rather than inferring a measurement from the generation label.
- What device is being discussed? Nanosheet, forksheet and CFET architectures are not interchangeable, and a proposed architecture is not proof that it is in production.
- Is the channel material established or exploratory? A proposal involving 2D materials or atomic channels signals a research direction unless manufacturing integration is also demonstrated.
- Does the result cover a transistor, an inverter, a process or a manufacturable chip? A device or circuit demonstration is narrower evidence than a production-process announcement.
- What is the status and schedule? Separate a research presentation, a roadmap target, a production schedule and high-volume manufacturing. A date for one named process generation does not establish a date for another.
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