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Start with the workload, not the sleep mode
Power choices make sense only in the context of what the system must do. First describe when it works, when it can wait, and what must remain available during each idle period. A device that wakes frequently to meet a tight response deadline has different constraints from one that can remain idle for long intervals.
- Duty cycle: Identify active periods, idle windows and how often the system moves between them.
- Response deadline: Record how quickly the device must respond to an event. A deeper sleep may save energy while increasing wake-up latency.
- Wake sources: List the timers, sensors, communication interfaces or other events that must be able to wake the system.
- State requirements: Decide what must survive an idle period and what can be reconstructed or reinitialized afterward.
These requirements help distinguish avoidable activity from necessary work. Reducing unnecessary computation, polling or time spent active can lower consumption without relying on a more aggressive sleep state. The relevant outcome is not simply minimum processor power, but whether the system completes its work within its energy, performance and response constraints.
Choose a power state by balancing energy, latency and retained state
Low-power modes are tradeoffs, not a universal ranking of “best” to “worst.” A mode that reduces consumption may take longer to exit or preserve less state, increasing restart work. Texas Instruments’ AM62x Processor SDK documentation says each mode should be evaluated against power consumption and wake-up latency; the numeric values are specific to that processor family and should come from the applicable device documentation.
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Arm’s 2021 guide to Cortex-M-based subsystems and SoC power-domain architecture describes component states that include running, clock-gated, retention and powered-down. These are useful concepts for reasoning about a design, not mode names or guaranteed options on every processor.
| Approach | What changes | Potential benefit | Key tradeoff to check |
|---|---|---|---|
| Reduce active work | Eliminate unnecessary processing or time spent active. | Less activity may reduce energy without changing the system’s sleep architecture. | Confirm that required work and deadlines are still met. No general power saving is established; it depends on the workload and device. |
| Clock-gate a component | Stop clocking a component while leaving it in a clock-gated state. | Can reduce activity in a component that need not run continuously. | Check whether the component must retain state or respond to an event while gated. Availability and numeric savings are device-specific. |
| Retain state in a low-power state | Keep selected state available while reducing activity or power to other parts of the system. | May avoid some restart or reinitialization work. | Identify which state is actually retained, what remains powered and the wake latency. Values depend on the device. |
| Power down a component or domain | Remove power from a component or power domain. | Can avoid powering circuitry that is not needed during an idle interval. | Determine what state is lost, what must be restored, and whether another component still depends on that domain. |
Before selecting a state, compare it with the real response deadline and the work needed after wake-up. Use the target processor’s datasheet and power-management documentation for mode-specific current, energy and latency values; do not transfer AM62x mode names or figures to a different processor.
Account for memory, peripherals and other bus masters
A sleeping CPU does not automatically put the rest of the system into a suitable low-power state. Clock control, memory retention, peripheral states and power-domain transitions are design choices. Arm’s 2021 guide emphasizes that a system’s components can have different states and that their power-domain dependencies matter.
In particular, the CPU may not be the only agent that needs access to shared resources. A DMA engine or another bus master may still need memory or an interconnect while the processor is idle. Powering down a resource too early can interrupt transfers or prevent a subsystem from operating as required.
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- Which CPU, DMA engine or other initiator may access each memory or interconnect resource?
- Which SRAM or other state must remain available, and which contents can be discarded?
- Which peripheral must remain powered to detect a wake event or complete a transfer?
- What sequencing or restart work is required when a domain changes state?
Use that map to determine what can be gated, retained or powered down during each idle window. Verify the behavior on the specific SoC: the fact that one component can sleep does not establish that its dependencies can also be turned off.
Compare candidate designs against the same requirements
A useful comparison keeps the workload and operating conditions the same for every candidate. Arm Education’s Efficient Embedded Systems Design Education Kit treats speed, cost and power as implementation evaluation dimensions. For an embedded power decision, add the state and availability constraints that determine whether a design can actually meet its application requirements.
| Comparison dimension | What to record | Why it matters |
|---|---|---|
| Power or energy | Average and peak power, or energy per completed task, for the same workload. | Average behavior, short peaks and energy per task answer different questions. Report the metric that matches the product constraint. |
| Wake-up and response | Wake-up latency and whether the response deadline is met. | A low-consumption state is not suitable if it prevents a required response on time. |
| Retained state | What survives, what is lost, and the restart or reinitialization work required. | Lost state can add time and energy after wake-up or affect application behavior. |
| Availability and dependencies | Required peripherals, wake sources, memory, DMA activity and interconnect availability. | A mode must leave the resources needed for idle-time work and wake-up available. |
| Performance and implementation cost | Relevant speed or throughput and the engineering effort or cost associated with the design. | Power efficiency is one design objective among several; a change should be judged against the product’s requirements. |
Use numeric mode values only when they apply to the exact processor, operating conditions and configuration being evaluated. Public guidance here does not establish one embedded-system benchmark or a generally applicable percentage of savings.
Independent reader supportYour contribution helps us test, update, and keep practical guides available for everyone.Measure the target design under realistic conditions
Estimate-based comparisons can miss current drawn by peripherals, memory, regulators or other board components. Measure the target design using a suitable instrument and a repeatable workload. The instrument and measurement method should fit the current range, required resolution, logging or sampling needs, bandwidth and circuit being measured; a generic multimeter is not automatically sufficient for board profiling.
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- Define the test: Specify the board and processor configuration, supply path, workload, operating conditions, wake pattern and power states.
- Choose the metric and instrument: Decide whether the question concerns average or peak power, energy per task, or another quantity. Select a current or power measurement setup whose range, resolution, sampling or logging and bandwidth suit that question.
- Run a repeatable workload: Use the same sequence and conditions for each design or mode. Include representative active and idle periods rather than measuring only an isolated sleep state.
- Record the measurement interval: State how long data was collected and how averages were calculated. Include relevant measurement uncertainty.
- Check application behavior: Confirm that wake sources, deadlines, memory use, peripheral activity and other required functions still work during and after the measurement.
The U.S. Department of Energy’s Federal Energy Management Program summarizes IEC 62301 guidance for measuring standby power in mains-connected end-user devices. In that standby-measurement context, a stable reading is defined as less than 5% variation from the mean over five minutes; fluctuating consumption is measured over time and divided by the measurement period to obtain average power. This is not a complete test standard for embedded boards, so use it only within its stated scope rather than treating its criterion as a universal embedded-device requirement.
Quick Recap
Common mistakes to avoid
- Choosing the deepest sleep by default: Lower consumption alone does not establish that a mode meets the response deadline or preserves necessary state.
- Measuring only the processor: Board-level behavior can include memory, peripherals and other components that remain active while the CPU sleeps.
- Ignoring non-CPU activity: DMA or another bus master may still need memory or interconnect resources during processor idle time.
- Comparing unlike tests: Different workloads, supply paths, operating conditions or measurement intervals make a power comparison difficult to interpret.
- Applying a family-specific value broadly: Mode behavior and numeric specifications belong to the relevant processor and configuration, not to embedded systems as a whole.
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