2D Semiconductors vs. Silicon: How Their Chipmaking Properties Compare

2D semiconductors offer a genuine scaling advantage, but silicon remains the practical chipmaking standard. A material such as molybdenum disulfide (MoS₂) can form a transistor channel only a few atomic layers thick, allowing a gate to control the channel more effectively as dimensions shrink. That advantage applies to one part of a chip. Contacts, dielectric interfaces, defects, wafer-scale growth, transfer, process compatibility, yield and circuit integration determine whether the device can be manufactured reliably. Silicon has decades of process knowledge, equipment, design rules and foundries behind it; 2D devices are only beginning to demonstrate integrated systems.

The fairest comparison is therefore not “which material has the higher mobility?” but “which platform can deliver uniform, connected and testable circuits at the required scale?” Recent prototypes include a 5,900-transistor MoS₂ RISC-V processor and a 1-Kb MoS₂ NOR flash module built above a commercial 0.13-μm CMOS die. Those results show meaningful progress and possible hybrid uses, not a replacement for high-volume silicon manufacturing.

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The short answer: a scaling opportunity versus a manufacturing platform

Two-dimensional (2D) semiconductors are crystals whose electrically active channel can be one or a few atomic layers thick. Transition-metal dichalcogenides (TMDs), particularly MoS₂, are the leading examples in transistor research. Silicon channels are much thicker in ordinary production structures, but silicon transistors benefit from mature architectures, carefully controlled interfaces and a complete complementary metal-oxide-semiconductor (CMOS) ecosystem.

At very short channel lengths, electrostatic control becomes difficult: the source and drain can influence the channel, and the gate has less authority over the current. An atomically thin 2D channel places the gate closer to essentially all of the channel volume. In principle, that suppresses unwanted short-channel behavior and permits aggressive scaling. It does not automatically produce faster, lower-power or cheaper chips. A high-resistance contact or a defective dielectric can overwhelm the benefit of a thin channel.

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A 2024 review describes the unresolved transition from laboratory devices to production as follows: “the way of moving 2DMs from ‘lab to fab’ remains unclear.” That is a statement about manufacturing integration, not a claim that 2D transistors are ineffective. The field has progressed from isolated flakes to circuits and system demonstrations, while the repeatability and economics required for a commercial wafer line remain unproven.

What counts as a 2D semiconductor?

Layered crystals and transistor channels

In a layered crystal, atoms are strongly bonded within each sheet and more weakly bonded between sheets. Researchers can isolate or grow sheets that are only one or a few layers thick. TMDs such as MoS₂ are semiconducting in those thin forms, so a gate electrode can switch their current in a field-effect transistor.

The useful property is not simply small thickness. The channel must have a suitable band structure, low enough defect density, stable contacts, an insulating gate interface and a process that places many devices in the correct locations. A laboratory flake with an excellent transistor does not establish that the same material can cover a wafer uniformly or survive every subsequent fabrication step.

Why silicon is the baseline

Silicon became the CMOS foundation because its electrical properties, native oxide, doping methods, thermal behavior and manufacturing supply chain can be controlled together. Production lines have process monitors, statistical controls, libraries of standard cells, packaging methods and design-automation tools built around silicon CMOS. Those capabilities are part of silicon’s chipmaking advantage even when an individual 2D transistor shows an attractive electrical result.

Side-by-side comparison of chipmaking properties

Where atomic thinness helps

Improved electrostatic control

For a gate to switch a transistor cleanly, its electric field must control the channel rather than allowing the source and drain to control it. In a 2D channel, the gate-to-channel distance can be comparable to the channel thickness. This geometry can reduce the volume in which unwanted charge accumulates and can help maintain switching behavior as the channel is shortened.

The benefit depends on the whole gate stack. A thick or defective dielectric, trapped charge, rough interface or poorly aligned gate can reduce control. Device geometry also matters: top-gate, bottom-gate, dual-gate and surrounding-gate structures expose different interfaces and parasitic capacitances. Consequently, “atomic thickness” describes an opportunity in the channel, not a guaranteed operating voltage, speed or leakage figure for a finished chip.

Potential for vertically stacked devices

Because a 2D sheet can be extremely thin, researchers can investigate placing transistors or memory elements above existing circuitry. Such stacking could add functionality without expanding the footprint of a silicon die. The thermal budget, alignment, contamination control and electrical connections of the stack determine whether that concept is practical. A layer that performs well in isolation may be damaged by the temperatures, chemicals or plasma steps used to build the next layer.

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Why contacts and dielectrics can erase the advantage

Contact resistance

The transistor channel is only one segment of the current path. Metal must inject carriers into the 2D layer and extract them again. The atomically flat surface has no dangling bonds at its basal plane, which can make low-resistance bonding difficult depending on the metal, edge structure and process. If contact resistance is high, the external circuit sees a slower and less energy-efficient device even when the channel itself has favorable transport.

Contact resistance also complicates comparisons of mobility. Extracted mobility can include or exclude contact effects depending on the measurement method and device geometry. A mobility number from one material, contact scheme and gate stack cannot be treated as a universal ranking against silicon.

Dielectric and interface traps

The gate dielectric must insulate the channel while coupling the gate field efficiently. Defects at the dielectric/2D interface can trap charge, shift the threshold voltage, create hysteresis and vary from device to device. Depositing a uniform dielectric on an atomically thin surface without damaging it is therefore a central process problem. Silicon’s mature oxide and interface engineering gives it a major practical advantage here.

Doping, spacers and patterning

Logic circuits require controlled p-type and n-type behavior, source and drain extensions, spacers and contacts with tight dimensions. Doping a 2D layer without damaging its lattice or creating unstable states remains an active area. Etching and cleaning must define the device while preserving a sheet that may be only one or two layers thick. These integration details can determine yield more strongly than the intrinsic band structure.

Material growth, transfer and wafer-scale uniformity

From a laboratory flake to a wafer

Many early demonstrations use mechanically exfoliated flakes: high-quality pieces selected from a larger crystal. That approach is valuable for discovering device physics but does not provide the area, placement or repeatability required for a chip line. Manufacturing needs a method such as chemical vapor deposition, epitaxial growth or another controlled synthesis route that produces the intended layer number and composition across a wafer.

Uniformity must cover thickness, grain structure, defects, contamination and electrical properties. A wafer can contain devices that work individually while still failing circuit-level specifications because their thresholds or contact resistances vary. Process control must detect those variations early and link them to growth conditions, transfer steps and patterning.

Transfer versus direct growth

Transfer can separate material growth from the target wafer, but it introduces wrinkles, particles, tears, residue and alignment errors. Direct growth avoids a separate transfer operation but must meet the thermal and chemical limits of the underlying wafer and circuitry. Neither route is automatically superior; the choice depends on the target stack, temperature budget, area and required defect density.

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Large-area synthesis and integration are repeatedly identified as barriers in the 2024 Nature Reviews Electrical Engineering review and the 2024 National Science Review review. Those reviews also emphasize that contacts, dielectrics, doping and spacers must be solved alongside growth rather than treated as later packaging details.

Process integration: replace silicon or add a 2D layer?

Why a wholesale replacement is difficult

A silicon replacement would need a complete transistor, interconnect, memory, packaging and design ecosystem. It would also need process windows wide enough for high yield and models accurate enough for circuit designers. Even if a 2D transistor offers better electrostatics, a production line would have to reproduce it billions of times while meeting reliability, contamination and thermal constraints.

2D devices may also require process temperatures or chemicals that conflict with ordinary CMOS steps. Conversely, the thermal cycles used in CMOS can damage a previously deposited 2D layer. A 2D process must therefore fit into a defined sequence, not merely demonstrate a working transistor on a convenient substrate.

Hybrid and BEOL strategies

A nearer-term strategy is to use 2D material where its thinness is most valuable while retaining silicon for established logic and support functions. Back-end-of-line integration places additional devices or memory above completed silicon circuitry, subject to the interconnect stack’s temperature and contamination limits. Hybrid designs can also partition functions: silicon supplies control and peripheral circuits, while a 2D layer supplies dense memory or a specialized transistor array.

This approach changes the comparison. The question becomes whether the added 2D module delivers enough density, energy or functionality to justify a new process, rather than whether 2D can duplicate every silicon transistor in a leading-edge processor.

What the latest circuit demonstrations actually prove

5,900-transistor MoS₂ RISC-V processor

A 2025 Nature paper reports a 32-bit RISC-V microprocessor built from 5,900 MoS₂ transistors. The work also includes a standard-cell library with 25 logic-unit types. This is important because it demonstrates coordinated device fabrication, logic-cell design, interconnection and processor operation rather than a single transistor.

The result should still be read as a prototype milestone. The transistor count and library size do not establish the density, defect tolerance, operating lifetime, wafer throughput or design ecosystem of a commercial processor line. They show that 2D devices can be assembled into a functioning general-purpose architecture at a meaningful research scale.

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1-Kb MoS₂ NOR flash above CMOS

A second Nature paper published 8 October 2025 reports a 1-Kb MoS₂ NOR flash module integrated above a commercial 0.13-μm CMOS die. The reported configuration achieved 94.34% yield in a full-chip test, 20-ns flash-cell operation and 0.644 pJ per bit.

Each figure needs its context. The 94.34% value is the authors’ full-chip result for this prototype, not a 2D logic-fab yield or an industry-wide manufacturing statistic. The 20-ns and 0.644-pJ figures describe the reported flash-cell operation and configuration. The demonstration’s central engineering idea is modular integration: the 2D memory and CMOS support circuitry retain different process and operating requirements while communicating through a designed interface.

How to interpret performance claims

Mobility is not a complete chip metric

Mobility describes how readily carriers respond to an electric field under a specified measurement method. It does not directly give clock frequency, energy per operation or system throughput. Contact resistance, capacitance, threshold variation, leakage, interconnect delay and circuit topology all affect a finished chip. The 2024 reviews discuss high mobility in selected 2D devices, but they also note that material, geometry, contacts and extraction methods differ. A universal “2D is faster than silicon” claim is therefore unsupported.

Separate intrinsic properties from process results

An intrinsic band gap or atomically thin lattice is a material property. A transistor’s on-current, subthreshold swing, retention, endurance or yield is a device-and-process result. A circuit’s speed and energy are system results. Comparing values is meaningful only when the test conditions, geometry, contact scheme, dielectric, temperature and measurement method are aligned.

Prototype yield is not production yield

A reported yield can refer to tested cells on one die, working dies in one run or another defined population. It does not automatically describe wafer-level yield, long-term reliability or the cost of making replacement wafers. Always identify the tested population and the process node or substrate used.

Cost, yield and reliability: what is known and unknown

The cited studies do not provide a matched commercial cost comparison between 2D and silicon manufacturing. They also do not establish a head-to-head volume-production yield benchmark. Silicon’s advantage is visible in its mature manufacturing economics and infrastructure, but a numerical silicon-versus-2D figure cannot be responsibly supplied from these sources.

For a real manufacturing decision, engineers would need at least:

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• Wafer-scale defect maps and electrical uniformity across multiple lots.
• Process capability data for layer thickness, contacts, dielectric deposition and alignment.
• Parametric yield, functional die yield and failure analysis at the intended circuit scale.
• Reliability results under temperature, voltage, cycling and data-retention stress.
• Throughput, equipment utilization, consumables and material-cost data.
• Design-rule, compact-model and process-design-kit support for circuit designers.

Until those data are available on comparable terms, 2D’s economic position remains an open engineering question rather than a demonstrated advantage.

A practical way to compare a 2D process with silicon

1. Define the job. Specify whether the target is logic, embedded memory, a sensor interface, stacked circuitry or another function. A material that is attractive for a low-temperature memory layer may not suit a high-current logic transistor.
2. Set the integration boundary. Decide whether the 2D device is built on a new wafer, transferred to a finished wafer or integrated above CMOS. This determines thermal budget, contamination controls and alignment requirements.
3. Measure the complete current path. Characterize contacts, channel, dielectric and interconnect together. Do not rank materials using channel mobility alone.
4. Map variability. Test many devices across the wafer and across process lots. Record threshold voltage, on-current, leakage, contact resistance and switching distributions.
5. Build representative circuits. Use ring oscillators, standard cells, memory arrays or the intended architecture. Circuit-level parasitics often expose problems hidden by isolated-device tests.
6. Test reliability and recovery paths. Include bias stress, thermal cycling, programming endurance where relevant and failure analysis. Determine whether a defective layer can be repaired, bypassed or replaced.
7. Compare the entire manufacturing flow. Account for growth, transfer, patterning, metrology, packaging, design enablement and yield learning, not only the transistor’s footprint.

What would count as a decisive advance?

Manufacturing evidence

A convincing advance would show repeatable wafer-scale material with controlled layer number and defect density, followed by uniform transistor parameters over many lots. The result would need a documented process window, not only a best-performing device.

Integration evidence

The process would need to coexist with practical CMOS temperatures, chemicals and interconnects, or clearly demonstrate a value-adding hybrid flow. Alignment, contact formation, dielectric deposition and patterning should be compatible with realistic design rules.

System evidence

Finally, circuits should demonstrate an application-level advantage under stated conditions: more memory per area, lower energy, a useful temperature range, faster operation at a defined voltage or a function that silicon cannot provide efficiently. The 5,900-transistor processor and 1-Kb flash module are steps toward this standard, but they do not yet supply commercial-volume evidence.

Bottom line for chipmakers and technology readers

2D semiconductors are best understood as a targeted scaling and integration technology. Their atomic thinness can give a gate strong control over a very short channel, and their low physical thickness creates possibilities for vertical or hybrid integration. Those are substantial reasons to keep developing them.

Silicon remains ahead on the properties that make chips manufacturable: controlled interfaces, repeatable wafer processing, mature contacts and dielectrics, established CMOS integration, design tools and production experience. For now, the evidence supports 2D transistors as promising additions for selected devices and hybrid systems, not as a proven high-volume substitute for silicon. The decisive comparison will come from uniform wafers, complete process flows, circuit reliability and production economics—not from atomic thickness or a single mobility number.

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