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DUV lithography can help make chip patterns finer than a single exposure can reliably print by dividing a dense design into simpler patterns, then combining them through alignment or spacer formation. This trades extra process steps and tighter process control for denser features. The key is that wavelength is only one limit on lithography: optical design and the way a pattern is built also matter.
How can 193 nm DUV print features smaller than its wavelength?
Lithography transfers a design onto a wafer. A reticle, or mask, encodes a pattern; a projection system reduces and focuses its image onto photoresist. Subsequent steps develop the resist and transfer its pattern into the material stack. Chip manufacturing repeats this process across many layers, and different layers can use different patterning flows.
A 193 nm DUV system does not simply draw one 193 nm-wide line at a time. The smallest pattern it can resolve depends on wavelength, the projection optics’ numerical aperture (NA), and process factors. Immersion DUV places water between the projection lens and wafer to increase NA. ASML says its highest-resolution DUV systems reach NA 1.35; that figure describes those systems, not every DUV scanner. ASML explains the lithography principles.
Multi-patterning provides another way to make a dense layout: ask each exposure or spacer sequence to create a simpler portion of it, then combine or transfer those portions into the wafer. A useful analogy is making a tightly spaced fence by placing alternating slats in separate passes—or by printing a coarser guide and using its sidewalls to create more slats. In a fab, however, this involves resist chemistry, deposition, etch, measurement and pattern transfer, not just repeated printing.
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What is double patterning?
In litho-etch-litho-etch (LELE), the dense target is split into two simpler subsets. The first is exposed and etched; the second is exposed and etched in a separate sequence. Together, the transferred patterns form the intended denser arrangement. Because the exposures are separate, their relative placement—or overlay—must be controlled. Layout decomposition and process integration also limit which shapes can be assigned to each exposure.
ASML describes multi-patterning as splitting complex patterns into simpler patterns that are printed separately and combined into a final pattern in its 2025 annual-report discussion. LELE is one version of that general idea.
How do SADP and SAQP make additional lines?
SADP: one spacer cycle
Self-aligned double patterning (SADP) starts with a lithographically formed core, often called a mandrel. A conformal material is deposited over it, then etched back so material remains along the core’s sidewalls. Removing the core leaves spacer lines. Those lines can be transferred into the layer below, producing a denser line pattern than the original lithographic seed alone.
Unlike LELE, SADP uses spacer formation to create the added lines rather than a second exposure to place a second subset. It still requires careful deposition, etch and pattern transfer. Imec compares litho-etch and self-aligned approaches as options with different cost-of-ownership, lithography-performance and process-complexity considerations. Imec’s comparison describes those trade-offs.
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Self-aligned quadruple patterning (SAQP) extends the spacer method. The first spacer pattern becomes a new core for another deposition-and-etch cycle, creating a denser line array. Imec describes an initial line becoming a four-times-denser-pitch result through this repeated sequence. That refers to pitch multiplication in a regular line pattern—not to every chip feature becoming four times smaller in every direction. Line ends and irregular shapes require additional block or cut patterning.
For a concrete, dated illustration, imec reported a 2017 demonstration combining immersion-based SAQP lines with EUV block exposure. The example patterned metal-2 at 32 nm pitch, or 16 nm half-pitch. It was a demonstration, not a universal production capability or a current node specification. Read imec’s account of the demonstration.
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Why do multi-patterning flows mix DUV and EUV?
A chip’s process is not necessarily all DUV or all EUV. A layer may use one method for regular lines and another for cuts or blocks; different layers may use different methods as well. In the imec example above, immersion-based SAQP formed the metal lines and EUV exposure defined block features before etch and metallization. This is why assigning a whole node a single lithography label can be misleading.
Imec’s 2019 comparison also discusses EUV multi-patterning and hybrid schemes. EUV does not automatically eliminate every need for pattern splitting or other additional patterning steps. Imec outlines the patterning options and integration trade-offs.
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What does multi-patterning add to manufacturing?
It exchanges optical difficulty for process complexity. More patterning operations create more places where variation can affect final dimensions or placement. The main control concerns depend on the method:
- LELE: overlay between exposures is critical because the separately printed subsets must land in the intended positions.
- SADP and SAQP: spacer dimensions, deposition uniformity, etch behavior and core removal affect the resulting line pattern.
- All approaches: added steps require process integration and measurement, and can affect throughput, defectivity, yield and cost of ownership.
- Irregular shapes: spacer flows are particularly suited to regular line arrays; block, cut or other patterning may be needed for line ends and less regular geometry.
Imec and Nova have reported developing scatterometry for SAQP process control to help identify sources of critical-dimension variation among line populations. ASML describes computational lithography as optimizing masks, scanners and processes to address physical and chemical effects and improve manufacturability and yield. These examples underline that multi-patterning is not simply taking extra exposures; it requires measurement and coordinated control of the full process. Imec and Nova describe the scatterometry work; ASML describes computational lithography.
Does EUV replace DUV multi-patterning?
No single technology is the universal winner. EUV’s shorter wavelength can print some patterns in fewer exposures or process steps than a DUV multi-patterning flow. In its 2025 annual-report discussion, ASML also notes that EUV systems consume more power. That is a vendor’s comparison, not a complete independent accounting of lifetime cost or environmental impact.
The choice depends on the layer and geometry, available equipment, pattern fidelity, process steps, control requirements, yield and cost of ownership. Imec reported 20 nm-pitch single-print demonstrations with High-NA EUV in 2025 and said single-print patterning reduces processing steps compared with multi-patterning. Those results show research progress, not proof that every such pattern is already used in volume production. Imec reports the High-NA EUV demonstration.
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Outbyte PC Repair FREEClear out junk files and repair common Windows errorsFree Scan →Outbyte Driver Updater FREEScan for outdated or missing drivers - takes under a minuteDriver Scan →For the same reason, a process-node label such as “5 nm” should not be read as the physical size of every feature on a chip. Node names do not specify a single line width, and a chip’s layers can use different patterning techniques. Publicly available sources cited here do not establish exact layer assignments for every fab or a universal cost-per-layer ranking.
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