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A Center for Technology & Statecraft (CTS) estimate, as summarized by AI Weekly on October 3, 2026, puts Chinese-owned fabs’ immersion DUV lithography inventory at 343 systems by early 2026, including about 270 ASML NXT:1980i tools. Those figures are attributed estimates, not an independently audited count of machines confirmed to be installed and running. DUV immersion tools can help produce advanced logic such as 7nm through multipatterning, but with significant process trade-offs. The cited account does not establish that this fleet enables HBM production.
What does the reported total of 343 DUVi tools mean?
AI Weekly’s October 3, 2026, account of a CTS report attributes an estimate of 343 immersion deep ultraviolet (DUV) lithography systems at Chinese-owned fabs by early 2026 to CTS. About 270 of the reported systems are identified as ASML NXT:1980i scanners. The summary does not provide a methodology or an operational-status breakdown, so the figures should not be read as a verified census of tools installed and running.
The same account relays CTS estimates that more than $13 billion was spent on NXT:1980i machines in 2024 and 2025, with about 90 systems in 2024 and 89 in 2025. These are estimates attributed to CTS through AI Weekly, not audited totals.
Can DUV immersion lithography make 7nm chips?
It can contribute to making advanced logic, including chips described as 7nm, by using multipatterning. That is not the same as printing every fine feature in one exposure or producing chips with economics equivalent to an EUV process.
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How multipatterning extends DUV
Lithography prints circuit patterns onto silicon wafers using light. Conventional DUV tools use 193 nm light; immersion systems place purified water between the lens and wafer to improve resolution. EUV uses a much shorter wavelength. With DUV, chipmakers can extend patterning capability by exposing a critical layer multiple times and combining the resulting patterns.
According to the American Enterprise Institute’s April 21, 2026, analysis, a modern 7nm logic chip involves more than 80 lithography steps, and roughly a dozen especially critical layers may be doubled or quadrupled using older DUV immersion tools. The tool is therefore part of a longer, more complex process—not a one-pass substitute for EUV.
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What the trade-offs look like
Repeated exposures consume scanner capacity and add process complexity. AEI estimates that SMIC’s DUV-based 5nm process costs 40–50 percent more than TSMC’s equivalent and may have yields as low as 20 percent. Those are the report’s estimates, not independently verified or industry-wide measurements. They illustrate why a node label alone does not establish comparable transistor density, throughput, yield, or cost.
| Comparison | DUV immersion with multipatterning | EUV |
|---|---|---|
| Patterning approach | Can require repeated exposures on critical layers; AEI says some layers in a modern 7nm logic process may be doubled or quadrupled. | Uses a much shorter wavelength; the cited AEI analysis does not give a comparable exposure count for a specific process. |
| Scanner time and process complexity | Repeated exposures use scanner capacity and add process complexity. | The cited AEI analysis does not quantify a like-for-like scanner-time comparison. |
| Cost and yield | AEI estimates SMIC’s DUV-based 5nm process is 40–50 percent costlier than TSMC’s equivalent, with yields as low as 20 percent. | The cited AEI analysis does not provide a directly comparable cost or yield figure for that process. |
Does the reported fleet show that Chinese fabs can make HBM?
No. The available CTS-related account repeats the HBM framing but does not explain or substantiate a manufacturing pathway linking the reported DUVi fleet to HBM production. The number of immersion scanners alone cannot establish that capability.
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The U.S. Bureau of Industry and Security’s December 2024 announcement confirms that certain high-bandwidth memory is a distinct export-control concern alongside specified semiconductor manufacturing equipment and related items. It does not verify that the reported DUVi tools enable HBM production. The evidence supports a qualified claim about DUV multipatterning for advanced logic; it does not support treating HBM capability as demonstrated.
Independent reader supportYour contribution helps us test, update, and keep practical guides available for everyone.What export-control claims are recommendations, not current rules?
AI Weekly attributes to CTS authors Nicholas Brown and Saif M. Khan a recommendation for “a China-wide ban on all DUVi exports.” That is a policy proposal, not an enacted ban. AEI separately recommends capability-based controls, a countrywide presumption of denial, and restrictions on servicing deployed tools; these, too, are recommendations.
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BIS announced controls in December 2024 covering specified semiconductor manufacturing equipment, software that can improve advanced equipment or help less-advanced machines produce advanced chips, certain HBM, and related foreign-produced items under specified Export Administration Regulations (EAR) rules. That announcement is background on measures introduced at that time, not a complete current licensing guide for every tool or shipment. Whether a particular DUVi system may legally be exported to China depends on the applicable current regulations and shipment details.
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How to read the headline accurately
- Inventory: 343 total immersion DUV systems and about 270 ASML NXT:1980i tools are estimates attributed to CTS through AI Weekly, not a confirmed count of operational machines.
- Advanced logic: Multipatterning lets DUV immersion contribute to advanced-node production, but extra exposures bring throughput, complexity, cost, and yield trade-offs.
- HBM: The cited material does not demonstrate that the reported fleet enables HBM production.
- Policy: The proposed China-wide DUVi restrictions are recommendations; BIS’s December 2024 announcement describes specified controls, not a blanket conclusion about every model or shipment.
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