Some links on this page are affiliate links: if you buy through them we may earn a commission, at no extra cost to you.
TSMC’s 2023 appeal to outsourced semiconductor assembly and test providers (OSATs) was not simply a request to buy more equipment. It was a call to build a larger, technically compatible network around TSMC’s 3DFabric advanced-packaging technologies—so partners could take on qualified portions of complex packages without making TSMC the industry’s only capacity bottleneck.
The immediate pressure was demand for CoWoS packaging used in AI and high-performance computing (HPC) chips. The bigger issue was coordination: substrates, routing, design tools, assembly, testing and reliability processes must work together. By 2026, larger package roadmaps and new investments by OSATs have made that ecosystem strategy more consequential, not less.
What TSMC asked OSATs to do
At its 2023 Open Innovation Platform event, TSMC described a specific next step for partners including ASE and SPIL: move beyond qualified substrates toward a more complete CoWoS service stack. TSMC wanted closer alignment in automated substrate routing, electronic design automation (EDA) tools and design-analysis flows, including 3Dblox and multiphysics analysis. AnandTech’s report of TSMC’s comments captures that request.
Free tools Windows power users keep installed
One-click scans. No signup required.
That distinction matters. TSMC was not asking for packages that merely look similar on a specification sheet. Compatible design and manufacturing flows help ensure that package routing, electrical behavior, heat, mechanical stress and assembly tolerances can be analyzed across the silicon, interposer, substrate and finished package. The 2023 comments describe a goal and partner work—not proof that every named OSAT could independently deliver every part of a production CoWoS package.
#1 Best Overall
- The world’s fastest gaming processor, built on AMD ‘Zen5’ technology and Next Gen 3D V-Cache.
- 8 cores and 16 threads, delivering +~16% IPC uplift and great power efficiency
- 96MB L3 cache with better thermal performance vs. previous gen and allowing higher clock speeds, up to 5.2GHz
- Drop-in ready for proven Socket AM5 infrastructure
- Cooler not included
Why CoWoS became a pressure point
CoWoS means “Chip on Wafer on Substrate.” It is TSMC’s 2.5D packaging platform: multiple dies, often compute dies and high-bandwidth memory (HBM), are integrated on an interposer and then mounted on a package substrate. TSMC says CoWoS has been in production since 2012, and reports that generative-AI demand has sharply increased demand for the platform since late 2022. TSMC’s CoWoS overview describes the technology and its development.
AI accelerators need more than fast compute cores. Their performance depends on moving data quickly between compute dies and large banks of HBM while managing power, signal integrity and heat. Integrating those components in a package can provide short, high-bandwidth connections, but it also turns the package into a demanding system-design and manufacturing job.
That creates a supply-chain bottleneck beyond wafer fabrication. A customer might secure logic dies and HBM yet still wait for interposers, substrates, package assembly or testing. More wafer output alone cannot solve a shortage at those later steps.
Quick wins for a faster PC:
Repair Windows errors before they cause bigger problemsFix Now →Scan for outdated or missing drivers - takes under a minuteDriver Scan →Clear out junk files and repair common Windows errorsFree Scan →Rank #2
- AMD Ryzen 9 9950X3D Gaming and Content Creation Processor
- Max. Boost Clock : Up to 5.7 GHz; Base Clock: 4.3 GHz
- Form Factor: Desktops , Boxed Processor
- Architecture: Zen 5; Former Codename: Granite Ridge AM5
What “expand capability” means in practice
Advanced packaging is not one machine or one process. An OSAT’s ability to support a particular product depends on capacity, compatible processes, engineering tools, testing and customer qualification.
- Capacity: Cleanroom space and suitable wafer-level packaging, flip-chip, bonding, molding, underfill, inspection and test equipment. Additional capacity must be of the right type; a conventional packaging line is not automatically equipped for a complex interposer-and-HBM assembly.
- Substrates and interconnects: Substrates need suitable routing, layer structures and dimensional stability. Interposer architecture, bumps and other fine-pitch connections must match the package design. TSMC’s 2023 comments specifically pointed to substrate qualification and automated routing as steps in the partner stack.
- Process fit: Assembly sequence, thermal and mechanical tolerances, electrical targets and reliability criteria must be compatible with the design and the relevant TSMC technology. “Advanced packaging” may mean 2.5D integration, fan-out, 3D stacking, hybrid bonding or system-in-package; capability in one does not establish qualification in another.
- EDA and analysis: Teams need tools and flows for package design and routing, signal and power integrity, thermal behavior, mechanical stress and warpage. TSMC’s 3DFabric Alliance includes EDA and analysis companies such as Cadence, Keysight, Siemens EDA and Synopsys, reflecting how much of the work is an engineering-ecosystem challenge, not just factory operations. The alliance’s member listing shows the breadth of that ecosystem.
- Testing and reliability: Multi-die packages make it harder to isolate a fault. A failure could originate in a compute die, HBM stack, die-to-die connection, interposer, substrate or assembly. TSMC said in 2023 that it was working with Advantest, Teradyne and Synopsys on high-speed die-to-die testing, with silicon validation then expected in 2024. That was a stated plan, not evidence that all OSATs had achieved complete chiplet-level test coverage.
- Qualification: A pilot line, an announced investment or a general “advanced packaging” offering is not the same as a customer-qualified, high-volume process for a specific package. Yield, reliability and test coverage need to be established for the actual design.
TSMC’s 3DFabric name covers a portfolio that includes CoWoS, InFO and TSMC-SoIC, with related services and ecosystem partners. The company continues to market integrated packaging and testing rather than stepping away from the field. TSMC’s advanced-packaging services page outlines its offering.
Why TSMC wants partners involved
TSMC’s own investment in packaging does not eliminate the reasons to involve OSATs. A broader qualified ecosystem can provide:
Rank #3
- Can deliver fast 100 plus FPS performance in the world's most popular games, discrete graphics card required
- 6 Cores and 12 processing threads, bundled with the AMD Wraith Stealth cooler
- 4.2 GHz Max Boost, unlocked for overclocking, 19 MB cache, DDR4-3200 support
- For the advanced Socket AM4 platform
- Capacity relief. Partners can add manufacturing resources when demand for TSMC-linked advanced packages grows faster than the available supply.
- More sourcing and service options. Depending on the package and qualification, customers may be able to source assembly, substrate or testing services from different providers rather than relying on a single end-to-end route.
- Geographic flexibility. Customers may value packaging nearer to other manufacturing steps or end markets. This can reduce concentration in one location, although it does not remove the need to qualify each site and process.
- Shared investment and ecosystem scale. OSATs can fund and operate parts of the backend supply chain, while coordinated design, substrate, memory and test partners make it more practical to develop complex chiplet packages.
These are complementary roles, not evidence that TSMC is abandoning advanced packaging or transferring its core technologies wholesale. TSMC continues to develop and offer 3DFabric; OSATs can expand the set of qualified services and capacity around it.
What’s actually slowing this PC down?
Pick the symptom - the matching free tool is one click away.
The OSAT business case—and its risks
Advanced packaging offers OSATs an opportunity to take on more technically demanding work, but the investment is not risk-free. Specialized equipment and cleanrooms require substantial capital. Packages can contain very expensive logic and memory dies, so an assembly defect can destroy more value than a failure in a simpler package. When a product contains many dies and interfaces, identifying the source of a yield or reliability problem can also be difficult.
Yield learning is design-specific, and qualification can take years. Substrate supply may remain constrained even after assembly lines expand. An OSAT could also face a mismatch between the capacity it funds and the customer volumes it ultimately receives: a customer may want a second source without promising enough committed demand to support the investment. Commercial returns therefore depend on utilization, contracts, process mix and execution; it would be misleading to assume that every advanced-packaging project earns more than traditional packaging.
Rank #4
- Pure gaming performance with smooth 100+ FPS in the world's most popular games
- 6 Cores and 12 processing threads, based on AMD "Zen 5" architecture
- 5.4 GHz Max Boost, unlocked for overclocking, 38 MB cache, DDR5-5600 support
- For the state-of-the-art Socket AM5 platform, can support PCIe 5.0 on select motherboards
- Cooler not included
Which OSATs are involved?
TSMC’s current 3DFabric Alliance listing includes ASE Group, SPIL, Amkor and STATS ChipPAC among OSAT members. Alliance membership indicates participation in the ecosystem; it does not mean the companies have identical processes or that every member is qualified to assemble every TSMC package. TSMC’s alliance page is the reference for its listed participants.
- ASE and SPIL: TSMC specifically discussed ASE and SPIL in the 2023 context of qualified substrates and expanding the CoWoS service stack. SPIL is part of the ASE Group ecosystem. ASE has announced a NT$17.6 billion investment in its K18B facility, targeting completion in the first quarter of 2028 and identifying CoWoS and system-in-package among its focus areas. In May 2026, ASE and WUS announced a Kaohsiung advanced AI packaging hub exceeding 113,000 square metres, with completion targeted for September 2029 and planned work spanning chiplet integration, CoWoS and FOCoS. These are announced plans and targets, not capacity already in production. ASE’s K18B announcement and its ASE/WUS announcement provide details.
- Amkor: Amkor is a major OSAT and a 3DFabric Alliance member. On July 23, 2026, it announced a $1.5 billion multi-year advanced-packaging and development agreement with NVIDIA to support expansion of U.S. advanced-packaging capacity. The announcement signals a substantial collaboration, but by itself does not identify every product, package flow, site or production volume covered. Amkor’s announcement sets out the stated agreement.
- JCET: JCET is another major OSAT with advanced-packaging ambitions. It should not, however, be conflated with the specific ASE/SPIL partners discussed in TSMC’s reported 2023 CoWoS comments or with a TSMC qualification that the available evidence does not establish.
TSMC’s Q3 2025 earnings-call transcript also described cooperation with a major OSAT building a facility in Arizona ahead of TSMC’s own planned Arizona advanced-packaging fabs. The quoted passage does not name the OSAT, so it is not sound to identify the company from that statement alone. The transcript provides the context.
The Tool Desk
Outbyte PC Repair FREEClear out junk files and repair common Windows errorsFree Scan →Outbyte Driver Updater FREEFix the driver behind crashes, sound loss and screen glitchesFind Drivers →How the picture changed by 2026
TSMC’s roadmap shows that the capacity challenge is moving alongside the technology. Its portfolio includes CoWoS-S, CoWoS-R and CoWoS-L. TSMC reports that CoWoS-R entered volume production in 2023 and its first 3.5-reticle CoWoS-L entered volume production in 2024. It says CoWoS-S supports interposers up to 3.3 times reticle size, approximately 2,700 mm². TSMC’s HPC roadmap reported certification of a 5.5-reticle CoWoS solution in 2025, with volume production planned for 2026; in May 2026, the company said it was producing 5.5-reticle CoWoS. TSMC’s CoWoS page and HPC roadmap cover those milestones.
Best Value
- Processor provides dependable and fast execution of tasks with maximum efficiency.Graphics Frequency : 2200 MHZ.Number of CPU Cores : 8. Maximum Operating Temperature (Tjmax) : 89°C.
- Ryzen 7 product line processor for better usability and increased efficiency
- 5 nm process technology for reliable performance with maximum productivity
- Octa-core (8 Core) processor core allows multitasking with great reliability and fast processing speed
- 8 MB L2 plus 96 MB L3 cache memory provides excellent hit rate in short access time enabling improved system performance
At its 2026 North America Technology Symposium, TSMC also described a 14-reticle CoWoS design planned for production in 2028, capable of integrating approximately 10 large compute dies and 20 HBM stacks. This is a roadmap target, not a guarantee that every customer can obtain the package or capacity on that date. TSMC’s symposium announcement states the plan.
The announced ASE facilities and Amkor-NVIDIA agreement point in the same direction: more investment and a stronger geographic dimension to advanced packaging. Expansion is evidence that the ecosystem is responding; it does not establish that shortages have ended. Bigger packages, more HBM, increasingly complex tests and customer interest in geographic diversity all create fresh capacity and qualification demands.
What customers should check before calling a source “compatible”
For a chip designer, buyer or supply-chain team, the meaningful question is not whether an OSAT uses the label “advanced packaging.” It is whether the provider is qualified for the specific product, process and production scale. Ask about:
Recommended Free Tools
- the package architecture and interposer type supported;
- HBM integration and the substrate’s routing, layer and warpage capability;
- the actual design, routing and multiphysics tools and data flows used;
- known-good-die handling, wafer sort, package test and die-to-die link coverage;
- yield, reliability and failure-localization evidence for the relevant design;
- high-volume readiness, available substrate supply and site-specific qualification;
- which stages each partner performs, and which stages remain dependent on TSMC or another supplier.
“Second source” can mean a second provider for one stage, not an interchangeable source for the whole package. Moving final assembly to an OSAT does not automatically relieve constraints in HBM, interposers, substrates or testing. Geographic diversification can reduce concentration risk but adds logistics and qualification work. And a larger package may enable more compute and memory, while also making warpage, thermal management, yield and testing harder.
The strategic point
TSMC’s 2023 request was an early signal that advanced packaging had become a shared manufacturing bottleneck. Its answer is not simply to outsource CoWoS, nor to make every OSAT a mirror of TSMC. It is to keep advancing its 3DFabric platform while bringing more partners into compatible parts of the design, substrate, assembly and test ecosystem. That approach can widen capacity and sourcing options, but only when engineering flows, qualifications, supply commitments and production economics line up.
Quick Recap
Product prices and availability are accurate as of the date/time indicated and are subject to change. Any price and availability information displayed on Amazon at the time of purchase will apply.
