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WeEn’s TOLT and TSPAK packages put SiC MOSFETs and Schottky diodes in surface-mount packages that transfer heat through an exposed metal surface on top of the device, rather than relying mainly on the PCB to carry heat to a heatsink. That can help when board-level cooling or power density is a constraint, but it does not guarantee lower system cost, lower switching loss, or better EMI by itself. The right choice depends on the exact device, heatsink interface, electrical layout, and manufacturing process.
WeEn introduced its top-side-cooled SiC product family in December 2024. The idea is straightforward: keep the device’s electrical connections on the PCB, while coupling its top metal surface to a heatsink. WeEn offers two package styles—leadless TOLT and gull-wing-leaded TSPAK—with SiC MOSFETs and SiC Schottky barrier diodes in the families. The package architecture is relevant to engineers evaluating power conversion; it is not a substitute for checking individual part data and system-level thermal and switching performance.
WeEn’s later technical article on TOLT and TSPAK and its current news and selection-guide listings provide a later portfolio reference than the original launch. The company lists a 2026 Selection Guide dated July 14, 2026. Confirm the exact part’s production status, ratings, and availability in that current guide and its datasheet; older portfolio ranges should not be read as a live ordering list.
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In a conventional bottom-side-cooled surface-mount power package, heat typically travels from the semiconductor die through the package into PCB copper, then spreads through copper layers and thermal vias before reaching a chassis or heatsink. The board can be a thermal bottleneck. A top-side-cooled package instead provides an exposed metal surface that can be coupled directly to a heatsink:
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- Drain-Source Voltage: 60V, Continuous Drain Current: 200mA
- High density cell design for low RDS(ON).
- Voltage controlled small signal switch.
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Top-side path: die → package thermal plate → thermal interface material → heatsink
Electrical path: package terminals → PCB pads and copper
This arrangement can free the board from acting as the primary heat spreader and can leave more freedom to route a compact electrical return path underneath the device. WeEn reported about 17%–19% lower thermal resistance than the relevant traditional bottom-side-cooled arrangement in its introduction. Treat that as a manufacturer-reported comparison, not a guaranteed improvement over every D2PAK, TOLL, or TO-247 design: actual results depend on the reference devices, board, heatsink, interface material, mounting pressure, airflow, and test conditions.
Top-side cooling still requires a deliberate thermal-mechanical design. The exposed surface must make effective contact with a suitable heatsink; interface thickness, flatness, clamping, package height, electrical isolation, and neighboring heat sources all matter. Poor contact can erase much of the package-level advantage.
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- Type: TO-92, N-Channel
- Drain-Source Voltage: 60V, Continuous Drain Current: 200mA
- High density cell design for low RDS(ON).
- Voltage controlled small signal switch.
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TOLT and TSPAK: similar cooling idea, different package choices
| Characteristic | TOLT | TSPAK |
|---|---|---|
| PCB electrical connection | Leadless bottom-side pads | Gull-wing leads soldered to the PCB |
| Heatsink connection | Exposed top metal plate | Exposed top metal plate |
| Likely design appeal | Compact, leadless construction; useful where low package parasitics are a priority | Leaded SMT format that may better suit mechanical compliance or established assembly practices |
| Trade-off to check | Footprint, solder inspection and rework, and heatsink integration | Lead contribution to parasitics, lead geometry, coplanarity, and mounting |
Both are surface-mount packages, but they are not interchangeable. WeEn describes TOLT’s leadless construction as an option for reducing package parasitic inductance; TSPAK’s leads may bring mechanical or implementation advantages, with some potential added inductance. The exact footprints, exposed-plate dimensions, lead details, clearances, and land patterns must come from the individual datasheet—not the package name.
What the SiC devices add—and what the package adds
SiC is used in power conversion where switching performance, efficiency, temperature capability, and power density matter. MOSFET conduction and switching behavior, and a Schottky diode’s characteristics, come from the semiconductor device. The exposed top thermal path comes from the package. Circuit layout, gate drive, heatsink design, and topology determine whether those component features become useful system outcomes.
A lower thermal resistance can support a lower junction temperature at a given loss, more output power within a thermal limit, a smaller heatsink, or a smaller die for a particular operating point. It does not directly mean lower switching loss. Switching loss depends on the selected device and operating conditions—including gate drive, switching frequency, current and voltage slew rates, commutation behavior, dead time, and parasitic inductance.
WeEn’s 2025 article also gives an illustrative TSPAK-versus-D2PAK calculation in which the thermal path allows a higher-resistance TSPAK MOSFET to meet a stated power-dissipation case, with estimated cost savings of 15%–20%. That is a WeEn example under its assumptions, not a generally applicable saving or proof that a higher-resistance device is the lowest-cost choice in a different design. Include switching behavior, gate-drive needs, heatsink and assembly costs, and actual supplier pricing in any comparison.
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- Low Drain-source on-resistance.
- High input impedance.
- High-speed switching.
- CMOS logic compatible input.
- Voltage Rated: 60V, Current: 200 mA.
Reported portfolio ranges are not individual-device specifications
WeEn’s product introduction described the following ranges:
| Family | MOSFET range in the overview | Schottky diode range in the overview |
|---|---|---|
| TOLT | 650 V; approximately 20–70 mΩ RDS(on) | 10–20 A |
| TSPAK | 650 V and 1200 V; approximately 12–150 mΩ RDS(on) | 10–40 A |
These are portfolio-level figures reported in the overview, not specifications for every part or confirmation that each part remains orderable. RDS(on) depends on test conditions, including gate voltage, current, and temperature; current and thermal ratings likewise depend on their stated conditions. Verify voltage margin, thermal resistance, dynamic data, package drawing, and ordering status in the exact part datasheet and current selection guide.
For example, the WNSC2M43065TB TSPAK datasheet identifies a 650 V device and gives a 74 A drain-current rating under its stated condition. It lists typical RDS(on) values of 43 mΩ at 15 V gate drive and 25 A, 25 °C, and 34.5 mΩ at 18 V under the datasheet’s stated test condition. Those numbers are specific to that device and test setup, not a shortcut for comparing the entire family. The datasheet also describes features such as Kelvin source, 0 V turn-off capability, 100% UIS testing, and suitability for parallel operation; check its detailed limits and conditions before relying on any feature in a design.
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Where the package architecture may fit
- Boost PFC: A direct heatsink path can help manage the MOSFET and diode thermal load. Their placement, commutation loop, and shared heatsink geometry still need to be designed together.
- Vienna PFC and other multilevel converters: Several devices may switch frequently, so thermal distribution and repeatable mounting become important across the stage.
- LLC converters: Primary- and secondary-side devices can benefit from thoughtful thermal symmetry and compact switching loops; the package alone does not determine converter efficiency.
- PV inverters and energy-storage systems: Sustained loading makes junction temperature, heatsink sizing, and thermal cycling central to the design.
- EV onboard chargers, e-compressors, DC-DC converters, and charging equipment: These are among the applications WeEn identifies. Automotive use requires verification of the exact part’s qualification and documentation.
- Server, telecom, UPS, and industrial supplies: High power density and automated assembly may make an SMT top-cooled approach worth evaluating, provided the mechanical and EMI constraints can be met.
Offering MOSFETs and Schottky diodes in both package families can help a designer build a power stage whose devices meet a common heatsink plane. Do not assume coplanarity from the family name: compare package drawings and tolerances for the exact parts and verify the assembled stack mechanically.
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Design-in checklist
Thermal and mechanical
- Calculate the complete junction-to-ambient path using the datasheet’s thermal parameters and boundary conditions. Do not confuse junction-to-case, junction-to-heatsink, and junction-to-ambient values.
- Choose a heatsink and interface material; specify contact area, compressed interface thickness, flatness, and clamping method.
- Check whether the heatsink needs electrical isolation and whether it affects creepage, clearance, or chassis grounding.
- Check package height and exposed-plate geometry across MOSFETs and diodes. Account for thermal cycling, solder-joint stress, and assembly tolerances.
Electrical and layout
- Compare VDS rating and transient margin, RDS(on) at the actual gate voltage and junction temperature, gate charge, gate-drain charge, and diode behavior.
- Check gate-voltage limits, recommended turn-on and turn-off voltages, Kelvin-source availability, short-circuit and UIS data, and parallel-device guidance for the exact device.
- Minimize the commutation loop, place the gate driver and high-frequency bypassing close to the device, and route a Kelvin-source gate return separately from the power-current path where available.
- Validate voltage overshoot, ringing, dv/dt behavior, and false turn-on at the device pins. A package cannot compensate for poor gate-loop routing, excessive common-source inductance, or inadequate decoupling.
Assembly, qualification, and sourcing
- Confirm the recommended land pattern, SMT placement and reflow requirements, inspection approach, and practical rework process with the assembler.
- Ask for current production status, samples, lead time, models, application guidance, and package reliability information.
- For automotive designs, verify qualification documentation for the exact part number. Do not infer AEC-Q101 status or automotive suitability from a family-level statement.
- Compare the exact datasheet and ordering status against the current selection guide. A 2024 guide and an original product announcement may not reflect current availability.
Common problems and how to investigate them
Ringing or EMI is worse than expected
Likely causes include a large commutation loop, long gate loop, poor Kelvin-source routing, insufficient local decoupling, unsuitable gate resistance, or measurement-probe inductance. First capture VGS and VDS with a short, low-inductance probe connection. Check the voltage at the device pins, reduce loop area, and move the driver and bypass capacitors closer. Tune turn-on and turn-off resistance separately. Consider a snubber only after correcting layout and measurement artifacts.
Thermal performance falls short
Check contact pressure, interface material and compressed thickness, heatsink coverage, flatness, and nearby heat sources. Measure package-top and heatsink temperatures separately, then recalculate the whole thermal path using the relevant datasheet conditions. A headline package resistance is not the same as the assembled junction-to-ambient result.
A device fails during switching
Possible causes include VDS overshoot, gate-voltage excursions, excessive di/dt, inadequate dead time or short-circuit protection, driver incompatibility, and parasitic turn-on of the opposite switch. Capture double-pulse waveforms, verify gate voltage at the device pins, and validate settings across temperature and production variation. Test at worst-case bus voltage and load current with appropriate transient margin.
MOSFET and diode do not mount evenly to one heatsink
Package height, exposed-pad geometry, heatsink flatness, or uneven clamping may be the cause. Compare the exact package drawings, confirm coplanarity before production tooling, and obtain the manufacturer’s mounting recommendations.
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How to compare alternatives
Compare complete device-and-package combinations, not package labels alone. Against D2PAK, TOLL, or TO-247, evaluate thermal resistance under comparable test boundaries, current-loop and package inductance, footprint, assembly method, heatsink access, isolation, mechanical tolerances, qualification, and supply status. WeEn’s claimed thermal improvement cannot establish a universal advantage over any of those packages.
ROHM announced its TSC3PAK top-side-cooled SiC MOSFET package in June 2026, including a listed 750 V lineup. This is another architecture to include in a shortlist where its voltage class and devices match the application. It is not a direct device-for-device comparison with WeEn’s cited 650 V and 1200 V TOLT/TSPAK ranges; compare exact ratings, switching data, dimensions, thermal conditions, qualification, and sourcing. See ROHM’s announcement.
Verdict: when to evaluate TOLT or TSPAK
Top-side cooling is worth evaluating when PCB heat spreading is limiting a design or a direct package-to-heatsink path could improve thermal margin or power density. TOLT is the more natural starting point when compactness and low package parasitics are priorities; TSPAK may be attractive where a leaded SMT format better fits mechanical or assembly constraints. Neither choice is automatic: prototype with the exact device, board, heatsink, interface, gate drive, and operating conditions, then validate temperatures and switching waveforms.
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