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TSMC’s blended wafer average selling price (ASP) rose by roughly 20% in 2025, according to an analyst estimate discussed during the company’s fourth-quarter 2025 earnings call. That does not mean TSMC increased the price of every wafer, process node, or customer contract by 20%.
The increase reflects a combination of higher prices for newer manufacturing technologies, a larger share of leading-edge production, strong AI-related demand, overseas-fab costs, and pricing intended to offset inflation in equipment, materials, and labor.
What the 20% figure actually means
Wafer ASP is the average revenue TSMC receives per wafer over a period. It is not the same as the negotiated contract price paid by a particular customer for a particular process.
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- TSMC raises prices for an existing or new process.
- The company manufactures more expensive wafers and fewer lower-priced wafers, changing the product mix.
The roughly 20% 2025 figure came from analyst Brett Simpson’s calculation, which was discussed during TSMC’s January 15, 2026 earnings call. TSMC’s finance chief explained that each new process node has a higher price and that the blended ASP rises as newer technologies become a larger part of production.
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- Beautiful microchip pattern structure made by the advanced copper technology
- 90~130nm minimum microchip feature Copper Characterization with TEOS or Black Diamond Low-k ILD on the single crystal silicon wafer
- The original value of un-polished wafer is above $500
- No guarantee for research and other applications
Therefore, the accurate conclusion is: TSMC’s blended wafer economics became significantly more expensive in 2025, but public disclosures do not prove a universal 20% price increase.
Leading-edge chips made up more of TSMC’s business
TSMC’s annual-report data show why mix mattered. Technologies defined by TSMC as 7nm and more advanced accounted for 74% of wafer revenue in 2025, up from 69% in 2024. The 3nm process alone represented 24% of total wafer revenue in 2025.
Those figures describe revenue mix, not the percentage of all wafers produced. Even so, the direction is clear: a larger share of TSMC’s business came from processes that generally command higher prices than mature nodes.
TSMC also said its 2nm process entered high-volume manufacturing in the fourth quarter of 2025, although it was not yet a major contributor to that year’s revenue. The company expected a faster 2nm ramp in 2026. TSMC’s total wafer shipments increased to 15.0 million 12-inch-equivalent wafers in 2025, from 12.9 million in 2024, so shipment growth and ASP growth were separate developments.
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- Wafer Pattern May Vary from the Product Images. Great to be used as gift, display object, exhibition, educating demonstration, testing, decoration or your collection
- Beautiful microchip pattern structure made by the advanced copper technology
- 90~130nm minimum microchip feature Copper Characterization with TEOS or Black Diamond Low-k ILD on the single crystal silicon wafer
- The original value of un-polished wafer is above $500
- No guarantee for research and other applications
TSMC’s 2025 annual report provides the underlying process-mix and shipment figures.
Why advanced-node pricing rose
New processes cost more
Every node transition requires costly research, new manufacturing equipment, process development, masks, and production ramp-up. TSMC has said that each new node carries its own higher price. As customers migrate from older technologies to 5nm, 3nm, and eventually 2nm, the average revenue per wafer rises even without an across-the-board increase on mature products.
A newer node can also deliver better performance per watt or more transistors per wafer. A higher wafer price does not automatically mean that it is economically worse for the chip designer; the relevant comparison includes performance, power consumption, yield, die size, and the customer’s product revenue.
AI and high-performance computing increased demand
AI accelerators, data-center CPUs, networking processors, and custom silicon rely heavily on advanced manufacturing and advanced packaging. TSMC’s annual report described robust demand for advanced technologies across smartphone, high-performance-computing, automotive, and Internet-of-Things applications.
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- 5 x 5 inches, 0.67 ounces, 0.03 inches thick. Some wafers are marked with alignment marks.
- The pattern is produced by light diffraction, and its reflective appearance changes with the viewing angle.
- Silicon wafers are fragile—please handle with care.
- Circuit details can be examined under a microscope.
When leading-edge capacity is heavily committed, a foundry has more pricing power. That supports higher prices, but demand and capacity utilization alone do not establish that a specific 2025 customer received a particular percentage increase.
Manufacturing costs increased
TSMC’s management also discussed pressure from inflation in tools, equipment, materials, and labor. Its second-quarter 2025 earnings call included questions about using pricing to offset foreign-exchange effects and the higher costs associated with overseas-fab expansion.
During the fourth-quarter call, TSMC indicated that recent pricing benefits had largely helped cover these cost increases. That is an important distinction: a higher ASP does not necessarily translate into an equivalent increase in profit margins.
Overseas fabs are structurally more expensive
Facilities outside Taiwan can have higher construction, labor, operating, and supply-chain costs. The Q4 2025 discussion specifically included the ramp of more expensive overseas fabs as a factor in the blended wafer-price question.
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- Multiple Diameter Options: Available in multiple diameters including 1, 2, 3, 4, 5, 6 and 8 inch silicon wafers
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- Research and Educational Applications: Commonly used in laboratories, universities, research institutes and educational environments
- Precision Polished Wafer Surface: Manufactured with smooth and stable wafer surfaces, available in SSP (Single Side Polished) and DSP (Double Side Polished) configurations for sample preparation, handling, and laboratory processing.
- Wide Laboratory Applications: Commonly used in universities, research institutions, material science laboratories, and scientific training programs for silicon material studies and experimental demonstrations.
However, the public evidence does not establish a universal foreign-fab surcharge or show that overseas production alone caused the 20% ASP increase. Customer, node, location, capacity, and contract terms can all differ.
Wafer price is not chip cost
A wafer contains many individual dies—sometimes hundreds or thousands, depending on die size. The cost of a finished chip depends on much more than the wafer invoice:
- Die size and the number of dies per wafer
- Manufacturing yield and the number of usable dies
- Photomasks and nonrecurring engineering
- Wafer testing and final testing
- Advanced packaging, interposers, substrates, and assembly
- High-bandwidth memory and other components
- Logistics, capacity commitments, and customer-specific engineering
The most useful manufacturing metric for a chip designer is often cost per good die, not simply the price of one wafer. A more expensive wafer can produce a competitive cost per usable die if it delivers better density or performance. Conversely, early production with lower yields can make the effective cost substantially higher.
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| Product category | Likely exposure | Why |
|---|---|---|
| AI accelerators and data-center chips | High | They often use leading-edge wafers and advanced packaging, both of which can be costly or capacity-constrained. |
| Premium smartphone processors | Moderate to high | New flagship generations commonly migrate to 3nm and future 2nm processes. |
| PC and server CPUs | Varies | Exposure depends on the process node, chiplet mix, packaging, and product generation. |
| Automotive and industrial chips | Often different | Many products use mature or specialty nodes, so they may not face the same pricing conditions as 3nm products. |
| Consumer electronics | Indirect | Retail impact depends on vendor margins, product strategy, inventory, component costs, and negotiated contracts. |
Apple, Nvidia, AMD, Qualcomm, and other major TSMC customers may be exposed when they use leading-edge processes, but their exact contract prices are not publicly verified. Large customers can negotiate volume discounts, reserved capacity, long-term agreements, and product-specific terms. Smaller fabless companies may have less bargaining power when capacity is tight.
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- Durable Design: Crafted from high-quality, transparent plastic for long-lasting use and easy visibility of contents.
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What the 2025 increase does not prove
- It does not prove that every TSMC wafer became 20% more expensive.
- It does not prove that every chip manufactured by TSMC cost 20% more.
- It does not mean Nvidia GPUs, Apple processors, or AMD CPUs became 20% more expensive to manufacture.
- It does not imply that phones, graphics cards, or computers became 20% more expensive at retail.
- It does not represent a publicly disclosed, universal TSMC price list for 2025.
Chip companies can absorb some cost increases, improve yields, alter product mixes, reduce discounts, renegotiate other components, or pass costs through gradually. Packaging constraints can also affect AI-chip costs independently of wafer fabrication. Wafer fabrication and advanced packaging should not be treated as one combined price unless a source explicitly does so.
Be cautious with reported node prices
Industry reports have cited estimated figures such as approximately $20,000 for a 3nm wafer and projections above $30,000 for 2nm. These are reported estimates or market expectations, not official TSMC disclosures establishing the price paid by every customer.
Similarly, reports of additional price increases in 2026 or 2027 should not be used as proof of a 2025 increase. For example, TrendForce reported in March 2026 that advanced-node capacity was expected to remain fully utilized and that selective increases were emerging. A separate Reuters report carried by Investing.com discussed possible increases of up to 10% from 2027. Those are later developments and should be kept separate from the verified 2025 ASP result.
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Bottom line
TSMC’s blended wafer ASP rose about 20% in 2025, according to an analyst estimate discussed on the company’s Q4 earnings call. The strongest explanation is a combination of higher pricing for newer process nodes, a shift toward leading-edge production, strong AI and HPC demand, and efforts to recover rising manufacturing and overseas-fab costs.
Calling the result a blanket 20% price hike would overstate the evidence. The figure describes an average shaped by both price and mix; the actual impact depends on the node, customer contract, yield, packaging, geography, and final product.
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