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Tigard is a versatile first-line hardware-hacking interface, not a universal key to every embedded bus. Its open-hardware design combines a dual-channel FTDI FT2232H, dedicated UART, switchable SPI/JTAG/I²C/SWD connectivity, level shifting from about 1.8 V to 5.5 V, and a logic-analyzer breakout. That covers many interfaces found on development boards, routers, appliances and microcontroller products, provided the target exposes usable pins and has not disabled or authenticated its debug paths.
The board is most useful when you want one labeled, voltage-aware tool instead of a collection of USB adapters, shifters, headers and cables. It does not discover undocumented pins, defeat secure boot, emulate every I²C device, or replace a high-speed logic analyzer. The official project documentation and designs are available at GitHub; hardware specifications and purchasing information are on Crowd Supply.
What problem does Tigard solve?
Embedded targets commonly expose several low-level interfaces, but investigating them usually means collecting separate USB-UART adapters, FT232H boards, level shifters, test clips and jumper wires. Tigard consolidates that setup. One FT2232H channel remains a dedicated UART, while the second channel is switched between SPI, JTAG, I²C and SWD. Labeled headers, included harnesses, USB-C and selectable target-voltage handling make it practical for bench work.
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- 【High-Speed 8-Channel Analysis】Captures digital signals at up to 24MHz across 8 channels, enabling precise debugging of complex protocols like I2C, SPI, and UART—ideal for advanced STEM projects without the limitations of basic 4-channel models.
- 【User-Friendly Design】Base module and breakout board simplify connections to breadboards, microcontrollers, and other setups.
- 【Logic Level Expansion Board】Breaks out all 8 channels to 2.54mm male pins and pads for alligator clips, enabling flexible and secure connections in diverse projects.
- 【Logic Level Breadboard Adapter】 Easily connects the logic analyzer to breadboards, providing direct and convenient access to all 8 channels for prototyping and testing.
- 【Dual USB Connectivity】Comes with both USB-A and Type-C cables for universal compatibility with older PCs, modern laptops, and devices, ensuring hassle-free plug-and-play across Windows, Mac, Linux, and Ubuntu.
What is on the board?
- FTDI FT2232H dual-channel USB interface.
- USB Type-C high-speed connection, listed at 480 Mbps.
- Dedicated UART channel and a shared secondary channel for SPI, JTAG, I²C or SWD.
- Directional level shifting for listed target voltages from approximately 1.8 V to 5.5 V.
- Selectable 1.8 V, 3.3 V or 5.0 V onboard supplies, or external
vTargetsensing/supply. - Mode switch for SPI/JTAG versus I²C/SWD operation.
- JTAG/SWD, SPI/I²C and UART headers, status LEDs and a logic-analyzer connector.
- Harnesses supplied with the board package shown by the seller.
The logic-analyzer connector is an observation point for an external analyzer; it is not a replacement for dedicated high-bandwidth instrumentation. Crowd Supply describes the associated BitMagic Basic analyzer as a way to monitor communications through PulseView.
Interface capability at a glance
| Interface | Typical use | Common software | Important limitation |
|---|---|---|---|
| UART | Boot logs, serial consoles, bootloaders and recovery shells | screen, minicom, picocom, PuTTY |
Requires correct baud, framing, polarity and TX/RX wiring |
| SPI | External flash, EEPROMs and compatible programmers | flashrom, PyFtdi, PySpiFlash |
In-circuit buses may be loaded or driven by the rest of the board |
| I²C | Sensors, EEPROMs, displays and board-management peripherals | PyFtdi/PyI2CFlash, LibMPSSE | Controller-only; no clock stretching; competing controllers can cause trouble |
| JTAG | Debugging, boundary scan, FPGA programming | OpenOCD, UrJTAG | Debug security, pinout and scan-chain state determine access |
| SWD | ARM Cortex-M debugging and programming | OpenOCD and target-specific tools | Needs correct 10-pin wiring, mode setting and often custom OpenOCD setup |
| AVR ISP / iCE40 | AVR programming and Lattice iCE40 programming | avrdude, iceprog |
Applies only to compatible target families and wiring |
UART: the quickest route to a console
UART is often the first interface worth testing because boot firmware may print diagnostics before the operating system starts. Connect Tigard TX to the target RX, Tigard RX to target TX, and ground to ground. The UART header also exposes target voltage and optional flow-control signals; do not connect a supply until you know whether the target is already powered.
After the device appears on the host, a documented example is:
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SPI flash: reading firmware safely
Tigard’s SPI header is arranged around common eight-pin flash layouts, making it suitable for SOIC-8 clips, sockets and EEPROM work. The project documents flashrom with this FT2232H example:
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- 🔍 Protocol Decoding & Data Extraction: Decode 30+ standard protocols (I2C, SPI, UART, CAN, etc.) to extract human-readable communication data, accelerating debugging.
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flashrom -p ft2232_spi:type=2232H,port=B,divisor=4Confirm the chip’s pin 1, voltage, chip-select, write-protect and hold connections before attaching a clip. In-circuit reads can fail because the processor or another device drives the bus, because the clip contacts poorly, or because board power is tied to Tigard accidentally. If identification is unreliable, remove or isolate the chip where appropriate, use a socket, lower the SPI rate and verify signals with an analyzer. Always make and verify a read-only backup before attempting an erase or write; supported chip IDs and write-protection behavior vary.
I²C works, but not as a universal I²C instrument
The I²C connector accepts JST-SH-style Qwiic and STEMMA QT cabling, which is convenient for sensors, EEPROMs and display controllers. Tigard operates as an I²C controller. It does not emulate a peripheral, does not support clock stretching, and may misbehave when another controller is active on the same bus. Pull-up resistors are normally supplied by the target; any weak onboard pull-ups should be treated as situational rather than guaranteed.
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Before starting, measure idle SDA and SCL levels, verify the voltage setting and check that no device is holding a line low. A hang can result from missing pull-ups, a stuck device, a competing controller, an unsupported stretched clock or a simple address error. Disconnect competing controllers, add correctly sized pull-ups where appropriate and reduce the bus speed. For peripheral emulation, clock stretching or demanding multi-controller work, use a purpose-built I²C analyzer or programmable instrument instead.
JTAG and SWD debugging
JTAG
JTAG can expose processor debug, boundary scan and FPGA programming when the target has an enabled, accessible chain. It is not a guarantee of unrestricted firmware access: readout protection, fused-off debug, authentication, unusual pinouts, incomplete chains and electrical contention can all block it.
The project’s OpenOCD example uses an FTDI adapter, channel 1 and a 2 MHz adapter speed:
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- The logic for each channel sampling rate of 24M/s. General applications around 10M, enough to cope with a variety ofoccasions; 8-channel
- Sampling rate up to: 24 MHz , can be 24MHz. 16MHz, 12MHz, 8MHz, 4MHz, 2MHz, 1MHz, 500KHz, 250KHz, 200KHz, 100KHz, 50KHz, 25KHz;
- The logic for each channel sampling rate of 24M/s. General applications around 10M, enough to cope with a variety ofoccasions;
- Input voltage range: -0.5V to 5.25V; Input Low Voltage: -0.5V to 0.8V; Input High Voltage: 2.0V to 5.25V
- Input Impedance: 1Mohm || 10pF (typical, approximate); Crystal: +/-20ppm, 24MHz
adapter driver ftdi
transport select jtag
ftdi vid_pid 0x0403 0x6010
ftdi channel 1
adapter speed 2000
ftdi layout_init 0x0038 0x003b
ftdi layout_signal nTRST -data 0x0010
ftdi layout_signal nSRST -data 0x0020Save that setup as the appropriate tigard-jtag.cfg, then run:
openocd -f tigard-jtag.cfgThe documented configuration requires OpenOCD 0.12 or later; older files may use deprecated commands. Target-specific reset wiring, adapter speed and transport settings still need adjustment.
SWD
SWD reduces ARM debug to SWDIO and SWDCLK plus ground, target voltage and optional reset. Tigard’s 10-pin arrangement follows the documented standard. A mode switch combines the relevant data lines to create bidirectional SWDIO, so orientation and switch position matter. SWD access depends on the microcontroller family, reset state, debug authentication and readout-protection configuration. The project notes that SWD may require building OpenOCD from source and following a target-specific configuration process.
A safe first connection
- Disconnect power from both Tigard and the target.
- Identify ground and signal pins from schematics, datasheets, board labels or continuity measurements.
- Establish the target I/O voltage; never infer it from connector appearance.
- Set the appropriate protocol mode and confirm pin-1 orientation.
- Connect ground first, then signal lines. For UART, cross TX and RX.
- Use
vTargetwhen the target is already powered. Select an onboard supply only when Tigard is intentionally powering a suitable standalone target. - Check that no two power supplies are being tied together and that no signal output will fight another output.
- Power the target only after inspecting the wiring, then begin at a low bus speed with read-only operations.
- Use a multimeter or external analyzer to confirm idle levels and transitions before writing or debugging.
- Power down before moving clips or rewiring. Keep a photograph and a verified firmware backup.
Do not attach to mains-connected or poorly isolated equipment. A 5 V setting can damage a 1.8 V target, and a missing ground, reversed connector or shorted SOIC clip can damage both the board and the interface.
Host software and setup realities
Tigard intentionally uses established FT2232H tooling rather than a proprietary application.
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- 16 channels dual-mode support: ①Stream mode captures and transfers data in real time for long sample duration; ②Buffer mode captures and stores data temporarily for high sample rate
- USB 2.0 Type-C interface with up to 16G sample depth in stream mode
- Support for adjustable threshold and shielded wires for a better, cleaner waveform
- 256Mbits on-board SDRAM memory with multiple buffer modes
- Compatibility with WinXP-Win10, macOS, and Linux, supporting nearly 100 protocol decoders, and being open-source on Github
| Task | Typical software |
|---|---|
| UART terminal | screen, minicom, picocom, PuTTY |
| SPI flash | flashrom, PyFtdi, PySpiFlash |
| I²C | PyFtdi/PyI2CFlash, LibMPSSE |
| JTAG | OpenOCD, UrJTAG |
| SWD | OpenOCD and target-specific tooling |
| AVR ISP | avrdude |
| iCE40 | iceprog |
| Signal observation | PulseView with an external logic analyzer |
On Linux, device permissions and udev rules may prevent access even when USB enumeration succeeds. Windows users must select the correct COM port. Check which FTDI channel a tool expects: one application may claim the UART channel while another requests channel 1 for JTAG or SPI. Close competing programs, confirm enumeration, and use the configuration syntax in the official repository rather than assuming one installation command works on every distribution.
What Tigard cannot do
- It does not natively analyze USB traffic, Ethernet, PCIe, MIPI, LVDS, DDR, RF or other high-speed/proprietary buses.
- It is not an analog measurement system or a high-bandwidth, deep-memory logic analyzer.
- It cannot guarantee firmware extraction from protected flash or a locked microcontroller.
- It cannot bypass secure boot, debug authentication or readout protection by itself.
- It cannot provide robust I²C peripheral emulation or clock stretching.
- It cannot operate every secondary protocol independently at the same time.
“Level shifting” also does not mean universal electrical compatibility. Open-drain behavior, pull-up voltage, current limits, reset sequencing, direction and board-level contention remain target-specific.
Independent reader supportYour contribution helps us test, update, and keep practical guides available for everyone.Choosing Tigard versus alternatives
| Option | Best fit | Trade-off |
|---|---|---|
| Cheap FT232H breakout | Lowest-cost users willing to wire and configure their own setup | Usually lacks integrated level shifting, dedicated UART, labeled headers, mode switching and harnesses |
| Bus Pirate | Interactive exploratory bus work | Less directly aligned with FT2232H debugger tooling and JTAG/SWD workflows |
| Glasgow Interface Explorer | Unusual protocols and programmable instrumentation | More capability and complexity than Tigard’s common-protocol focus |
| GreatFET One | Python-programmable, extensible security research | More custom host-side work; fewer of Tigard’s dedicated, ready-labeled connections |
| Dedicated debugger or logic analyzer | Vendor IDE integration, advanced trace or high-speed capture | Typically narrower purpose and may require additional adapters for other buses |
Choose Tigard when several common interfaces, open hardware and integrated voltage handling matter more than advanced protocol generation. Choose Glasgow or GreatFET when custom scripting and unusual interfaces dominate. Add a dedicated debugger or analyzer when target speed, trace depth or vendor integration is the real requirement.
Price, availability and useful accessories
On August 18, 2026, Crowd Supply listed Tigard with harnesses at $49, plus $8 U.S. shipping or $18 worldwide shipping, with orders shown as shipping September 8, 2026. These are date-stamped listing conditions, not a permanent MSRP. A European purchasing option is listed at 1BitSquared; verify VAT, stock, shipping and returns at checkout.
The same Crowd Supply page listed BitMagic Basic at $35 on that date. It is useful for confirming wiring and signal activity, but remains an external analyzer rather than a replacement for high-speed instrumentation. Plan for a SOIC-8 clip, JST-SH cables, an ARM 10-pin SWD cable, a multimeter, current-limited bench supply and magnification if your work involves flash chips or fine-pitch headers.
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- ★The logic for each channel sampling rate of 24M/s. General applications around 10M, enough to cope with a variety ofoccasions; 8-channel.
- ★Sampling rate up to: 24 MHz , can be 24MHz. 16MHz, 12MHz, 8MHz, 4MHz, 2MHz, 1MHz, 500KHz, 250KHz, 200KHz, 100KHz, 50KHz, 25KHz.
- ★Input voltage range: -0.5V to 5.25V; Input Low Voltage: -0.5V to 0.8V; Input High Voltage: 2.0V to 5.25V.
- ★Input Impedance: 1Mohm || 10pF (typical, approximate); Crystal: +/-20ppm, 24MHz.
- ★UART, SPI, IIC and other communication debugging, let you get twice the result with half the effort. 24M sampling rate, can automatically analyze UART, IIC, SPI and many other standard protocols.
Failure modes and recovery
No UART output
Check ground, TX/RX crossover, voltage setting, serial device, baud/framing and flow control. Determine whether output occurs only during reset. If necessary, observe receive-only with an analyzer and consider disabled, encrypted or non-UART signaling.
SPI reads fail
Recheck pin 1, clip contact, chip-select, write-protect, target power and flash support. Isolate or remove the chip, slow the clock and inspect the bus with an analyzer.
I²C hangs
Measure idle SDA/SCL, verify pull-ups and voltage, disconnect another controller and look for a stuck-low line. Use a specialized I²C instrument if clock stretching or peripheral emulation is required.
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JTAG or SWD cannot detect a target
Verify pinout, mode switch, ground, target reference, reset wiring, FTDI channel and OpenOCD configuration. Lower adapter speed and check whether debug is fused off or authenticated.
The target becomes unstable
Power down immediately and inspect for wrong voltage, tied supplies, reversed connectors, missing ground or output contention. Recovery is not guaranteed; current limiting and a backup made before any write are your best safeguards.
Use it only on authorized hardware
UART consoles, debug ports and flash contents can expose credentials, proprietary firmware, personal data or safety-critical controls. Restrict experiments to equipment you own or are explicitly authorized to test, and isolate devices whose failure could create a hazard.
Quick Recap
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