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StarFive announced on December 7, 2021, at the RISC-V Summit in San Francisco that it had begun delivering its 64-bit Dubhe processor-core IP to customers. That meant customers could integrate the licensed CPU design into their own chips; it did not mean a Dubhe-branded processor or computer was available to buy. StarFive described a superscalar, deeply out-of-order core and reported performance figures from customer evaluations, but the public announcement did not include independent benchmark validation or identify the customers.
What StarFive announced
Dubhe was presented as a high-performance RISC-V CPU core for chipmakers and other customers designing their own systems-on-chip (SoCs). StarFive said it had officially delivered the IP to customers and cited interest from data-center, PC, mobile, high-performance networking, and machine-learning markets. Those were target markets and areas of customer engagement—not evidence that Dubhe-powered products had shipped in each one. StarFive’s announcement also called Dubhe the world’s highest-performance RISC-V core; that is the company’s positioning, not an independently established industry ranking.
CPU IP is a design, not a retail processor
Processor IP is a reusable design that a customer licenses and integrates into a chip. The customer must combine it with the rest of an SoC—such as memory controllers, interconnects, accelerators, security blocks, and peripherals—and then verify, manufacture, and enable the finished system. The usual path is:
- Receive or license the CPU IP.
- Integrate it into an SoC and verify the design.
- Complete physical design and send the chip for fabrication (tape-out).
- Bring up the resulting silicon and develop its software.
- Qualify and ship a finished product.
IP delivery is an early milestone in that process. StarFive’s 2021 statement does not establish that Dubhe had entered mass production, appeared in a commercially available chip, or was sold as a board or computer. It also did not name customers or publish license prices, royalties, or support terms.
#1 Best Overall
- Flexible MCU Board: Incorporate the ESP32-C3 32-bit RISC-V chip, operating up to 160 MHz, mounted multiple development ports,
- Developer Friendly: Compatible with Arduino IDE, MicroPython, CircuitPython, PlatformIO, ESP IDF, Zephyr, Matter, ESPNow, Meshtastic, WLED, ESPHome, Home Assistant, Ubidots
- Outstanding RF performance: Complete Wi-Fi functions and Bluetooth Low Energy, while supporting communication over 100m with anFL antenna
- Elaborate Power Design: 4 working modes as low as 44 μA in deep sleep mode, while supporting lithium battery charge management
- Thumb-sized Design: 21 x 17.5mm, Seeed Studio XIAO series classic form factor
Original Dubhe: published specifications and claims
| Area | What StarFive said in 2021 |
|---|---|
| Product | 64-bit RISC-V CPU-core IP |
| Execution design | Superscalar and deeply out of order |
| ISA and extensions | RV64GC, plus B (bit manipulation), N (user-level interrupts), V 1.0 (vectors), and H (hypervisor) |
| Process and frequency | Up to 2 GHz on TSMC’s 12 nm process |
| Reported benchmarks | 8.9 SPECint2006/GHz, 6.6 DMIPS/MHz, and 7.6 CoreMark/MHz |
| Target markets | Data centers, PCs, mobile devices, high-performance networking, and machine learning |
The extension set indicated an ambition beyond basic embedded processing. Vector instructions can help with data-parallel work such as signal processing or scientific computing; the hypervisor extension is relevant to virtualization; bit-manipulation instructions can benefit some low-level integer tasks. But an instruction-set feature is not a guarantee of application performance. Compilers, operating systems, hypervisors, optimized libraries, execution-unit throughput, and the wider SoC all matter.
Likewise, advertising vector or hypervisor support does not by itself show that production software was mature. The 2021 announcement did not document Linux, Android, hypervisor, compiler, or vector-library readiness for original Dubhe.
Rank #2
- CH32V003 Development Minimum System Board for Nano RISC-V CH32V003F4U6 Chip TYPE-C USB 22Pin
- on-board 24MHz Crystal oscillator
- Power by TYPE-C USB
How to read Dubhe’s performance numbers
StarFive attributed the figures to customer evaluations. Its announcement did not provide a complete methodology or independent benchmark report, so the numbers should be treated as vendor-reported results, not as independently reproduced scores. The release does not specify, among other details, compiler versions and flags, operating-system configuration, cache and memory setup, core count, voltage and clock conditions, or whether measurements came from FPGA, emulation, or silicon. It also does not establish that the SPECint2006 result was a standardized, publishable SPEC submission.
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The metrics are not interchangeable. SPECint2006 is a broader integer benchmark, though it is an older generation of SPEC testing. Dhrystone and CoreMark are synthetic benchmarks and do not stand in for modern application workloads. A result per GHz is useful for one kind of comparison, but it does not show total performance, energy use, or performance in a customer’s system. A claimed 2 GHz on TSMC 12 nm cannot be assumed for another process, cache configuration, voltage, or chip design.
Rank #3
- The ESP32-C3 SUPERMINI is positioned as a high-performance, low-power, cost-effective IoT mini development board, suitable for low-power IoT applications and wireless wearable applications
- It is equipped with a rich set of interfaces, including 11 digital I/Os that can be used as PWM pins and 4 analog I/Os that can be used as ADC pins.
- It supports four serial interfaces, including UART, I2C, and SPI.
- The ESP32-C3 features a 32-bit RISC-V CPU, including an FPU (Floating Point Unit) capable of 32-bit single-precision
- Package: 2PCS ESP32-C3 MINI Development Board ESP32 SuperMini ESP32 C3 WiFi Module
Nor do these figures support a definitive comparison with a named Arm core: the announcement supplies no controlled, independently reproducible, like-for-like comparison. Real performance depends on memory bandwidth, cache behavior, interconnect contention, software, and thermal limits as well as the CPU core.
Where Dubhe fit in StarFive’s later CPU-IP portfolio
StarFive’s later announcements describe a growing family. They should not be read as proof that the original 2021 core was simply renamed or that all family members share its specifications.
Rank #4
- ESP32-C6 WiFi 6 microcontroller development board adopts ESP32-C6-WROOM-1-N8 module, which is equipped with RISC-V 32-bit single-core processor, up to 160MHz main frequency, built-in 8MB Flash
- Integrates WiFi 6, Bluetooth 5 and and IEEE 802.15.4 (Zigbee 3.0 and Thread) wireless communication, with superior RF performance
- Integrates rich peripherals including SPI, UART, I2C, I2S, LED PWM, SDIO and other interfaces, compatible with the pinout of ESP32-C6-DevKitC-1-N8 development board, more convenient to use and expand a variety of peripheral modules
- Onboard CH343 and CH334 USB HUB chips, supports USB and UART development at the same time via a USB-C port
- Comes with online examples and tutorials for ESP-IDF development environment
- Dubhe-90: StarFive’s current product page describes a commercial 64-bit RISC-V core with RV64GCBH, an 11-stage-plus pipeline, five-issue superscalar execution, deep out-of-order execution, and multicore cache coherence. The company lists 9.4 SPECint2006/GHz. These are Dubhe-90 claims, not specifications to retroactively assign to original Dubhe. Dubhe-90 product page.
- Dubhe-83: In a December 2024 announcement, StarFive described an RVA23-oriented design with a 10-stage-plus pipeline, three-issue superscalar execution, deep out-of-order execution, Vector 1.0 support, and a claimed 8.5 SPECint2006/GHz. It said the core was offered in single-, dual-, or quad-core clusters and supported by bare-metal and Linux SDKs and an Eclipse-based IDE. StarFive’s Dubhe-83 announcement.
- Dubhe-80 and Dubhe-70: StarFive later positioned the 80 as an energy-efficiency-oriented design and the 70 as an ultra-low-power out-of-order core. StarFive’s portfolio announcement.
The company says it delivered Dubhe in 2022 and subsequently introduced the Dubhe-90 and Dubhe-80 lines. The sequence shows continued portfolio development, but does not by itself establish commercial shipment volumes or adoption of any particular core.
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1Clear out junk files and repair common Windows errors2Fix the driver behind crashes, sound loss and screen glitches3Repair Windows errors before they cause bigger problemsWhat a chip designer should check before licensing CPU IP
A headline benchmark is only one part of an IP evaluation. A prospective licensee should ask for evidence tied to its intended workload, process, and product schedule.
Best Value
- Ample PSRAM Storage – The development board offers 8MB PSRAM, providing substantial extra memory for handling more complex tasks, large data buffers, and advanced processing.
- Enhanced Multi-Tasking Capability – With the additional 8MB PSRAM, the ESP32-C5-WIFI6-KIT can efficiently manage multiple protocol stacks simultaneously, ensuring smooth operation in multi-tasking IoT environments.
- Support for Medium-Load Applications – The 8MB PSRAM allows the ESP32-C5 to handle medium-load applications more effectively, making it ideal for scenarios requiring real-time data processing or continuous communication.
- Seamless Performance – The increased memory improves the overall performance and responsiveness of the device, particularly when running applications with larger memory footprints or more demanding computations.
- Future-Proof for Complex Projects – With 8MB of PSRAM, developers are better equipped to build scalable, high-performance solutions that support both current and future IoT use cases, offering flexibility for future-proofing designs.
- ISA and software: Confirm the exact supported profile and extension versions, and whether the required compilers, Linux or RTOS, hypervisor, libraries, debug, trace, and profiling tools are available and maintained. Ask about vector width and software support rather than assuming the V extension alone assures acceleration.
- Microarchitecture: Request details such as pipeline and issue width, out-of-order window, branch prediction, load/store capacity, integer, floating-point and vector throughput, cache behavior, memory ordering, MMU, and interrupt handling.
- Integration package: Establish what is included or separately licensed: RTL, verification collateral, models, test suites, debug modules, interrupt handling, bus interfaces, coherent interconnect, IOMMU, formal-verification support, and security or safety features.
- PPA evidence: Seek results for the intended foundry and process, clock, voltage range, core count, cache configuration, and thermal envelope. A result on one process node is not a portable guarantee.
- Commercial and lifecycle terms: Clarify upfront fees, royalties, minimums, engineering support, source access, customization and derivative rights, geographic or export restrictions, maintenance, bug fixes, and security-update commitments.
Public materials do not disclose original Dubhe’s license price, royalty rate, full implementation configuration, or named customers. RISC-V is an open instruction-set architecture; that does not make every RISC-V CPU implementation open source. Dubhe is presented as commercial licensable IP.
Other commercial RISC-V IP to evaluate
For a chipmaker comparing licensed processor designs, alternatives include other IP vendors—not consumer RISC-V boards. The right comparison depends on workload, process, software support, integration package, and commercial terms.
- SiFive: Its portfolio covers embedded through high-performance and data-center-oriented cores. The company describes a licensing model involving upfront fees and royalties based on chip selling price, but does not publish a fixed price list. SiFive core IP and data-center solutions.
- Andes: The AX45MP is a 64-bit multicore IP design described as dual issue, with up to eight cores, cache coherence, MMU, and optional custom extensions. It may suit efficient multicore, embedded-Linux, or configurable applications, but it is not a direct performance equivalent to a five-issue, deeply out-of-order design. Compare the exact core, vector options, process, and workload. Andes AX45MP.
- Codasip: The company emphasizes configurable RISC-V processors and processor-architecture licensing, including custom instructions and PPA tailoring. That flexibility can be valuable when differentiation is required, but customization adds verification, software, and schedule work. Codasip processors and architecture licensing.
These vendors generally require an enterprise inquiry for licensing; public pages do not provide a common, fixed price basis for comparison. A buyer should request current documentation and evaluate software status, support commitments, and implementation results on equivalent terms.
Quick Recap
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