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SNUG India 2025 put three connected shifts in focus: AI-assisted chip engineering, modular silicon built from multiple dies, and India’s expanding role in the semiconductor industry. The in-person Synopsys Users Group conference took place on July 10, 2025, at the Sheraton Grand Bengaluru Whitefield. Its message was not that AI can design a chip on its own or that India has completed a domestic semiconductor ecosystem; it was that chip design is becoming more automated, package-aware, and system-level.
What was SNUG India 2025?
SNUG stands for Synopsys Users Group, a Synopsys-hosted conference series for semiconductor and electronic-design professionals. The events bring users, technical experts, partners, and company leaders together to discuss design, verification, implementation, intellectual property, packaging, and related electronic design automation (EDA) workflows. Synopsys describes its SNUG program as covering areas including AI-driven chip design, multi-die systems, 3D design and packaging, verification, and silicon lifecycle management (Synopsys SNUG).
That makes SNUG a practical, vendor-centered user conference—not a neutral academic symposium. Its sessions can offer useful engineering knowledge and customer experience, while also illustrating how Synopsys positions its tools and ecosystem. Synopsys characterized the Bengaluru event as the 26th edition of SNUG India and later said it drew more than 3,000 attendees and featured more than 60 technical presentations. Those are company-reported figures, not independently audited attendance data (Synopsys event recap).
The event’s advertised keynotes made the connection between engineering change and national ambition explicit. Synopsys Chief Product Development Officer Shankar Krishnamoorthy spoke on “Re-engineering Engineering in the Era of Pervasive Intelligence”; Tata Electronics Foundry CTO Raj Nair spoke on “Building India’s Vibrant Semiconductor Future” (Synopsys event promotion). The titles signal themes, not proof of a new product or a completed Indian manufacturing ecosystem.
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AI is becoming an engineering layer, not a replacement for engineers
In semiconductor design, “AI” can describe several different things that should not be conflated:
- AI for chip design: machine-learning or generative-AI methods applied to EDA tasks, such as exploring design choices, assisting with RTL or verification, optimizing physical implementation, supporting debugging, or retrieving relevant engineering knowledge.
- Chips designed for AI: processors, accelerators, memory systems, interconnects, and packages built to handle AI workloads.
- AI agents for engineering: systems intended to carry out sequences of engineering tasks, rather than only autocomplete code or answer a question.
At its most useful, AI can help engineers search a large design space, automate repetitive work, reuse accumulated knowledge, and spot promising power, performance, and area trade-offs earlier. But these are assistance and productivity goals. Generated RTL, constraints, or optimization choices can be plausible and still be wrong; a result optimized for one metric can worsen another. Engineers still need to validate outputs, cover corner cases, and complete the normal verification and signoff process.
There are practical risks as well. Proprietary design data may be sensitive, especially when a workflow sends it to an external service. Teams need to understand data handling, repeatability, and how a tool reached a result. Synopsys used the phrase “agent engineers” in its event recap, but that is company terminology, not evidence that an autonomous system can take a product through a production-quality tapeout. A conference demonstration or reported use case should not be treated as a universal performance guarantee.
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What “modular chips” means—and why the package matters
“Modular chips” is an umbrella phrase, not one standardized architecture. It may refer to chiplets or other separately designed dies assembled into a system; 2.5D integration using an interposer; 3D stacking; heterogeneous integration of components built using different processes; or reusable subsystems and IP that are modular in design but not separate physical dies.
In a chiplet-based system, for example, a company might combine compute, I/O, memory-related functions, or specialized acceleration in distinct dies and connect them inside a package. This can let designers choose different process technologies for different functions, reuse validated components, and create product variants without redesigning one enormous monolithic die. Modular architectures were among the themes identified in coverage of SNUG India (EE Times’ event coverage).
The trade-off is that the design problem moves beyond the individual die. Die-to-die links must deliver adequate bandwidth and latency without excessive power. Engineers must plan power delivery, heat removal, mechanical behavior, test, repair, package yield, and security. Multiple suppliers also raise questions about interoperability, component provenance, and who is responsible when a system assembled from separate dies fails.
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Chiplets therefore do not guarantee a lower-cost or better product. For a small-volume design, advanced packaging and integration may cost more than the reuse saves. A monolithic die may remain the stronger choice when simplicity, power, latency, or a single supplier’s control matters most. The right architecture depends on workload, production volume, process options, packaging availability, test strategy, and lifetime support.
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India’s opportunity is broader than fabrication—but not yet the whole value chain
India is important to semiconductor engineering through its large technical workforce, established design-services and verification operations, multinational research and development teams, and technology hubs such as Bengaluru. Domestic interest in fabless companies and system design, along with government support for the sector, adds to the effort to expand India’s role. The Tata Electronics keynote at SNUG made the manufacturing and ecosystem ambition part of the event’s discussion.
Still, strength in chip design does not automatically create leading-edge manufacturing capability. A durable semiconductor ecosystem also needs process engineering, materials and equipment supply, packaging and testing, reliable utilities and logistics, skilled fab operators, design IP, customers, and sustained capital. Advanced AI products bring additional dependencies, including access to leading manufacturing processes, advanced packaging, high-bandwidth memory or alternatives, and robust networking and supply chains.
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It is more accurate to ask which parts of the value chain India can build and scale than to describe it simply as either a design center or a future manufacturing power. Design and verification, fabless product development, foundry production, packaging and testing, equipment and materials, and workforce development are distinct capabilities. Progress in one does not prove maturity in all the others. The SNUG sources establish that India’s semiconductor future was a conference theme; they do not establish specific fab schedules, process nodes, production volumes, investment totals, or commercial customer commitments.
SNUG India should also not be confused with SEMICON India 2025. The two events had overlapping subjects—such as AI, research, and semiconductor growth—but different organizers and purposes. SNUG was Synopsys’ user conference; SEMICON India had its own separate official agenda (India Semiconductor Mission agenda).
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Why the themes suit Synopsys’ strategy
AI adds complexity to chip design, while multi-die systems increase the number of interactions that must be modeled across dies, packages, and systems. That creates demand for EDA tools and engineering environments that span more than an isolated design step. Synopsys’ broader SNUG messaging has emphasized AI, 3D design and packaging, software-defined systems, and collaboration with major technology companies (Synopsys announcement on its 2025 Silicon Valley conference).
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There is also a customer and ecosystem function to SNUG. Customer and partner presentations can share workflows, surface practical issues, and show how teams use a vendor’s tools. That offers value to users and helps build loyalty to the toolchain. It is useful context when assessing event messaging: a presentation may demonstrate an application, but does not by itself establish general savings, performance, or suitability for every design team.
Synopsys’ acquisition of Ansys, announced at approximately $35 billion, forms part of the company’s broader effort to connect chip design with engineering simulation and system-level design. Its relevance to SNUG India is strategic context, not proof that a fully integrated Synopsys-Ansys workflow was launched or demonstrated at the Bengaluru event. The available event sources do not establish which Ansys products or integrations, if any, were shown there.
What engineers should take from the discussion
- Plan at system level. For multi-die designs, package, power, thermal, test, and interconnect decisions need to influence architecture early—not arrive as late-stage fixes.
- Keep verification central. AI can assist with design and debug, but generated output and automated optimizations still need disciplined review, coverage, and signoff.
- Build package expertise. As more products depend on heterogeneous integration, packaging, signal and power integrity, thermal design, and test become core engineering concerns.
- Evaluate AI tools against real workflows. Teams should ask what task is automated, what data the system uses, how results can be checked and reproduced, and where human approval remains necessary.
- Assess India’s progress by capability. Design talent, fabless products, fabrication, packaging, and supply chains should be tracked separately rather than rolled into one broad claim of self-sufficiency.
What SNUG India 2025 did not prove
- It did not establish that AI can independently complete chip design or replace engineering verification.
- It did not show that chiplets are cheaper or superior for every product.
- It did not demonstrate that India has achieved end-to-end semiconductor self-sufficiency.
- Synopsys’ attendance and presentation totals were company-reported, not independently audited.
- It was not SEMICON India, and announcements from that separate event should not be attributed to SNUG.
The signal from Bengaluru
SNUG India 2025 was less about a single breakthrough chip than a change in how the industry expects chips to be engineered: with AI-assisted workflows, modular silicon, advanced packaging, and closer chip-to-system integration. It also reflected India’s growing importance as an engineering and talent base and its ambition to expand further across the semiconductor value chain. That direction is significant; how quickly manufacturing, packaging, and domestic product businesses scale remains an open question.
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