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SK hynix’s August 1, 2022 announcement introduced a 96GB DDR5-based CXL memory sample for servers—not a new kind of desktop DIMM or a product shown to be broadly available. The module paired 24Gb DDR5 DRAM with a CXL controller, an EDSFF E3.S form factor and a PCIe 5.0 x8 link. The story later advanced: in April 2025, SK hynix said it had completed customer validation of a 96GB CXL 2.0 CMM-DDR5 product. That validation is a meaningful qualification milestone, but it does not by itself establish general availability or universal server compatibility.
What SK hynix announced
The 2022 development sample was designed to add memory capacity to compatible servers over CXL, rather than occupy a conventional CPU-attached DDR5 DIMM slot. SK hynix said the module used 24Gb DDR5 DRAM made with its 1anm process, had 96GB capacity, and incorporated CXL controllers. It used the enterprise-oriented EDSFF E3.S form factor and supported a PCIe 5.0 x8 connection. SK hynix worked with Montage Technologies on CXL memory design and verification. SK hynix’s original announcement described samples and set mass production in 2023 as a target; that forward-looking target is not evidence that production occurred on schedule.
| Detail | 2022 sample |
|---|---|
| Capacity | 96GB |
| Memory | 24Gb DDR5 DRAM, 1anm process |
| Form factor | EDSFF E3.S |
| Host interface | PCIe 5.0 x8, carrying CXL |
| Controller | CXL controller integrated into the module |
| Status at announcement | Development samples; mass production planned for 2023 |
DDR5 is the memory; CXL is how the host reaches it
DDR5 describes the DRAM technology on the module. Compute Express Link (CXL) is the interconnect and protocol layer that lets a host communicate with compatible devices, including memory expanders. CXL uses the PCIe physical and electrical infrastructure, but it is not simply another name for PCIe or a claim that the attached memory performs like local DDR5. The CXL specification defines three related protocols:
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1Fix the driver behind crashes, sound loss and screen glitches2Clear out junk files and repair common Windows errors3Scan for outdated or missing drivers - takes under a minute- CXL.io handles device discovery, configuration, interrupts, DMA and other I/O functions.
- CXL.cache lets a device access host memory while maintaining coherency.
- CXL.mem lets a host processor access memory attached to a CXL device.
For this kind of module, the practical idea is that the server can access DRAM beyond its ordinary local memory configuration through a CXL connection. See the CXL 2.0 specification for the protocol and platform-level features.
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- Capacity: 16GB(2 x 8GB)
- Tested Frequency Profile 1: PC5-48000 (6000MT/s)
- Tested Timings: 36-46-46-110
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- On-Die ECC
Why add memory over CXL?
Local DDR5 attached directly to a CPU is normally the first memory tier: it is close to the processor and generally favored when low latency is essential. But a server’s local memory capacity is constrained by its supported DIMMs, slots, CPU memory channels and board design. CXL memory offers another route to capacity, potentially allowing operators to add memory without redesigning the processor’s local-memory subsystem.
That can matter when workloads—such as in-memory databases, analytics, virtualization, scientific computing or some AI workloads—are constrained by capacity, or when memory demand varies among servers. An added tier can help consolidate workloads or reduce the need to provision every host for its theoretical peak demand. It may also enable more flexible resource allocation. Those are architectural possibilities, not guaranteed savings or speedups: total cost and performance depend on hardware, utilization, software and workload behavior.
CXL memory is not automatically equivalent to local DDR5. Access may involve a link, and sometimes a switch, before reaching the memory device. Effective latency and bandwidth depend on the CXL generation, link width, topology, controller, contention, placement and access pattern. A workload with frequent latency-sensitive random accesses may gain less than one that chiefly needs additional capacity. CXL is best understood as a way to extend or reorganize a memory hierarchy, not as a promise of faster memory in every server.
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- Reliable Performance Features: Features on-die ECC for real-time error correction, built-in PMIC for stable power delivery, and energy-efficient 1.1V operation for improved reliability
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Expansion, switching and pooling are different setups
“Expandable memory” can describe several architectures. A device may be directly attached to a compatible host port. With a CXL switch, a host can connect to additional devices; more elaborate switching and system management can support allocating pooled capacity across hosts or logical systems. CXL 2.0 adds switching and memory-pooling capabilities, alongside features including managed hot-plug, security enhancements, persistent-memory support, error reporting and telemetry. It is specification-level backward compatible with CXL 1.0 and 1.1, but that does not guarantee that any particular combination of device, server, firmware and operating system will work together.
The 2022 SK hynix sample should not be mistaken for a complete pooled-memory system. Pooling requires compatible devices and switches where applicable, plus host hardware, firmware, management and operating-system support. A CXL fabric manager may run on a switch, host or baseboard-management controller, depending on the system design. A directly attached module can provide expansion without automatically making its capacity shareable among multiple servers.
Why EDSFF E3.S matters—and why it is not a desktop DIMM
EDSFF E3.S is an enterprise form factor intended for server and data-center equipment. Its use signals a module designed for server infrastructure, rather than a standard DDR5 UDIMM or a laptop memory module. It does not fit an ordinary DIMM slot. Nor does the PCIe 5.0 x8 interface make the device interchangeable with a typical PCIe SSD or graphics card: the host must support the relevant CXL device and memory protocols, not merely have a PCIe slot. Physical fit or PCIe signaling alone is not sufficient for compatibility.
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- On-Die ECC
HMSDK: software is part of the memory system
Alongside the sample, SK hynix announced the Heterogeneous Memory Software Development Kit (HMSDK), intended to improve access to CXL memory and offer system-performance and monitoring functions under different operating conditions. The company said it planned to distribute HMSDK as open source in the fourth quarter of 2022. That was the announced plan; it should not be read as proof that every planned release or feature arrived on that exact schedule.
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In its 2025 update, SK hynix said HMSDK had been integrated into Linux and optimized for CMM-DDR5. It described software that could move data between conventional DRAM and CMM-DDR5 according to access frequency. This is the kind of tiering logic that can help keep frequently accessed data close to the CPU while using expanded memory for other pages. It does not mean every Linux distribution will automatically make optimal placement decisions. Kernel and firmware support, CXL enumeration, NUMA policy, vendor integration and workload locality all matter. “Integrated into Linux” is not the same as a guarantee of support in every distribution or upstream kernel configuration.
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- August 1, 2022: SK hynix announced its first DDR5 DRAM-based CXL memory samples: 96GB, 24Gb DRAM, EDSFF E3.S, PCIe 5.0 x8 and an integrated CXL controller. The company stated a 2023 mass-production target.
- 2024: At CXL DevCon, SK hynix reported a demonstration with up to 50% more bandwidth and 100% more capacity than systems equipped only with DDR5 DRAM. These are company-reported results from a demonstration, not universal CXL performance figures. SK hynix’s account of the demonstration gives the context.
- April 23, 2025: SK hynix said it had completed customer validation of a 96GB CXL 2.0 CMM-DDR5 product. It also said a 128GB version, using 32Gb DDR5 built on its 1bnm process, was still undergoing customer validation. The validation announcement reported 36GB/s processing, a 50% capacity increase and a 30% bandwidth improvement over previous DDR5 modules in the company’s stated server configuration.
These milestones are not interchangeable. A sample demonstrates a design; a demonstration shows a system configuration; customer validation indicates qualification with a customer. None of those statements alone proves broad commercial availability, volume shipments, a public retail price or compatibility with every server. The 2024 “up to” results and 2025 figures also come from different company-described configurations and should not be combined into a single generalized performance claim.
Rank #4
- DDR5 5600MHz PC5-44800 288 Pin Unbuffered Non-ECC 1.1V CL46-46-46-90 Single Rank 1Rx8 based
- Speeds at 5600MHz with 1.5x faster than DDR4, Capacity 16GB Containing 1x16GB module
- JEDEC DDR5 On-die ECC (ODEC) to Improve error checking capability and provide better accurate data-processing
- High-Quality Power Management IC (PMIC) Onboard to ensure stable power transfers and lower power consumption at only 1.1V
- Compatible with DDR5 Desktops, Not compatible with DDR4 motherboards
What a server operator should verify
A deployment takes more than buying a module with the right capacity. Before planning a CXL memory installation, confirm all of the following with the server vendor and device supplier:
- Host capability: Does the CPU and root port support CXL, the required device type and the relevant CXL generation?
- Link and slot qualification: Does the server provide the required PCIe generation, lane width and qualified EDSFF E3.S location?
- Firmware: Do the BIOS/UEFI and platform firmware enumerate and configure the device correctly?
- Operating system and software: Are the kernel, drivers, NUMA policies and any memory-tiering tools supported for this exact platform?
- Topology and management: Is the device direct-attached, switched or pooled? If switched, what switch and fabric-management stack are required?
- Operations and reliability: Are error reporting, telemetry, security, hot-plug behavior and support lifecycle adequate for the workload?
- Workload evidence: Have application-level performance and capacity benefits been measured on the intended configuration, rather than inferred from link speed or a vendor demonstration?
For a buyer, the normal route is through a server OEM, cloud provider or systems integrator, not a consumer retail listing. The supplied product announcements do not establish a public price or self-service retail channel for this specific module.
Who should care?
The technology is relevant chiefly to cloud and data-center operators, server OEMs, systems integrators, and teams running capacity-hungry AI, HPC, analytics, virtualization or in-memory applications. It is less compelling where the server already has enough local memory, minimum latency is paramount, or the platform and software stack lack validated CXL support. Desktop and laptop buyers should not expect to install this E3.S module in a consumer PC.
For most workloads, qualified local DDR5 remains the simpler choice when it provides sufficient capacity and low latency is the priority. CXL DRAM is an additional option for appropriately designed systems, not a universal replacement. Component makers such as Montage Technology also supply CXL memory-expander controllers for module and system makers; a controller component is not itself a finished, ready-to-install memory product.
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