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SK hynix announced on September 26, 2024, that it had begun mass production of a 36GB HBM3E stack made from 12 DRAM dies. The stack raises capacity per HBM placement by 50% over the company’s 24GB 8-high design, while the thinner dies are intended to keep package height roughly comparable. This was a manufacturing milestone—not a retail memory launch or proof that a particular GPU uses the part.
What SK hynix announced
SK hynix said it had started volume production of its 12-layer, or 12-high, HBM3E product on September 26, 2024. The company described it as the first 12-layer HBM3E product in mass production. It reported a memory-operation speed of up to 9.6Gbps and said it expected to supply customers by the end of 2024. Those are the company’s announcement and forecast, not evidence that every customer received the product on that schedule. SK hynix’s announcement is the primary source for those specifications and claims.
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“12-high,” “12-layer” and “12H” describe the same basic idea: twelve DRAM dies stacked vertically in one HBM package. The important distinction is between a stack’s capacity and the total memory installed in an accelerator. The announced figure is 36GB per stack, not 36GB for an entire GPU or server.
How 12 dies add up to 36GB
SK hynix’s stack uses twelve 3GB DRAM dies: 12 × 3GB = 36GB. Its earlier 8-high configuration, using the same capacity per die, provides 24GB. That makes the 12-high stack a 50% increase in capacity per placement.
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For scale, four such stacks would total 144GB, six would total 216GB, and eight would total 288GB. These are arithmetic examples, not claims about any named accelerator. Actual system capacity depends on the number of stacks a platform is designed to use and the final product configuration.
The challenge: fitting more layers into the package
Adding four dies could make a stack taller, but height is constrained in an accelerator package, where HBM sits alongside the processor and must fit within the package and cooling assembly. SK hynix said it made each DRAM chip 40% thinner than in the previous design so twelve dies could fit within approximately the same package-height envelope as its eight-layer product.
Thinner dies are more demanding to handle and stack. In a taller assembly, alignment, bonding, warpage, heat removal and package-level reliability all matter. A denser stack is useful only if it can be manufactured consistently and integrated within mechanical and thermal limits. Die thinning does not by itself establish that a product is slower or less reliable; it increases the importance of process control and qualification.
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SK hynix also credited its Advanced MR-MUF process—a molding and bonding approach used in HBM packaging—with helping manage the taller, thinner stack. The company claimed the process improves heat dissipation by 10% over the previous generation and helps control warpage. That 10% figure is a SK hynix comparison, not an independently established result for every system or cooling setup.
What 9.6Gbps does—and does not—tell you
The 9.6Gbps figure is a signaling-speed specification, not the total bandwidth of an accelerator. To calculate bandwidth, the interface width and implementation also matter; to estimate aggregate accelerator bandwidth, the number of stacks and the platform design matter as well.
As a point of comparison, Micron describes its HBM3E implementation as using a 1,024-bit interface and delivering more than 1.2TB/s per placement at pin speeds above 9.2Gbps. Those are Micron’s figures for its implementation and should not be transferred automatically to SK hynix’s stack. A headline speed alone is not enough to determine a system’s total memory bandwidth.
Why more HBM capacity can help AI workloads
Higher capacity gives an accelerator more fast local memory for model weights, intermediate data and other working sets. Depending on the workload and software configuration, that can help fit a larger model, support a larger batch or longer context, or reduce the need to move data to system memory. In some cases, greater capacity can also change how many accelerators are needed to meet a memory-capacity target.
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1Fix the driver behind crashes, sound loss and screen glitches2Clear out junk files and repair common Windows errors3Scan for outdated or missing drivers - takes under a minuteThese are possibilities, not guaranteed performance gains. A workload limited by compute rather than memory capacity may see little benefit from extra HBM. Capacity and bandwidth are separate: increasing one does not automatically increase the other. Model partitioning, parallelism, software and the rest of the system all influence what can run and how fast.
SK hynix illustrated the capacity with an example involving a four-stack system and a 70-billion-parameter Llama 3 model. Its accompanying read-rate illustration is a company-provided example, not an independent benchmark of end-to-end AI performance.
Independent reader supportYour contribution helps us test, update, and keep practical guides available for everyone.How the 2024 announcements compare
The milestone depends on what “first” means. Samsung announced a 36GB HBM3E 12H design on February 27, 2024, and said mass production was planned for the first half of that year. Samsung’s announcement also cited bandwidth of up to 1,280GB/s. An announced design and production plan are not the same milestone as confirmed mass production.
On September 25, 2024, Micron said it had begun shipping production-capable 36GB HBM3E 12-high units to key industry partners for qualification, with output expected to ramp in early 2025. Micron also claimed a 20% power advantage over competitors’ 24GB HBM3E 8-high solutions; that is a vendor comparison, not a neutral, independently verified comparison across all products. Micron’s disclosure describes its shipment and qualification milestone.
SK hynix’s September 26 announcement was specifically a claim that mass production had begun. In short: Samsung announced its design earlier, Micron disclosed production-capable units sent for qualification, and SK hynix announced mass production. Design announcements, samples, qualification shipments, production starts and broad customer availability are different steps; they should not be collapsed into a single “first to market” claim.
Mass production is not the same as a product you can buy
HBM is integrated into advanced accelerator packages. It is not a DIMM, a standalone upgrade for a desktop graphics card, or a component that a server owner can install in an existing system. GPU, ASIC and accelerator-platform makers must design for the memory, package it with the processor, and qualify the resulting hardware.
Consequently, a production announcement does not prove high-volume shipments to every customer, qualification on a named GPU, or retail availability. Public information does not establish a complete customer list for SK hynix’s specific 36GB 12-high part. Do not infer that a particular NVIDIA, AMD or other accelerator uses it without a direct confirmation. The end-of-2024 supply date was SK hynix’s stated expectation at announcement, not proof of universal availability.
There is no credible public retail list price for the individual stack. Commercial terms are generally negotiated in the accelerator supply chain, and the relevant product for most buyers is a complete accelerator platform—not the HBM package by itself.
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Why the announcement mattered
The technical point was not simply that the stack holds more memory. SK hynix’s engineering challenge was to add four dies and 50% more capacity while keeping stack height within a comparable package envelope, then manufacture and qualify it for use in demanding accelerator systems. Whether that translated into a particular customer product depended on qualification, yields, supply allocation and the accelerator’s package design.
The announcement is best understood as a September 2024 supply-chain milestone. SK hynix later reiterated that month as the start of mass production in its 2024 retrospective. It does not, on its own, establish the newest HBM available in 2026 or identify which current accelerators contain SK hynix memory.
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