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A safe DMA buffer is not a special Linux buffer type. It is memory that a device can address correctly, access only during an explicitly defined ownership period, and release without corrupting memory or exposing old data. Safety also depends on cache coherency, mapping lifetime, device isolation, and synchronization between shared users.
Linux drivers should therefore use the generic DMA API rather than passing CPU pointers or guessed physical addresses to hardware. The right design depends on whether the transfer is short-lived, persistent, fragmented, shared between devices, or exposed to userspace.
What “safe DMA” means
DMA lets a device read or write memory without the CPU copying every byte. That improves throughput, but it also gives hardware a path into system memory. A buffer is safe only when all of the following conditions hold:
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1Scan for outdated or missing drivers - takes under a minute2Clear out junk files and repair common Windows errors3Fix the driver behind crashes, sound loss and screen glitches- Addressability: the device receives a valid DMA address within its supported address range.
- Ownership: the CPU does not access memory while the device may still read or write it.
- Coherency: cache maintenance is handled correctly on non-coherent systems.
- Lifetime: the allocation and mapping remain valid until the device has definitely stopped using them.
- Isolation: the device cannot DMA into unrelated memory.
- Confidentiality: recycled memory is cleared before it crosses into another process, VM, device, or security domain.
- Sharing: fences and CPU-access rules serialize access when several users share one allocation.
These are separate properties. dma_alloc_coherent() can address cache visibility, for example, but it does not provide lifetime management, bounds checking, fencing, or protection from a malfunctioning device.
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Linux’s DMA API abstracts the difference between CPU virtual addresses, physical memory, and device-visible addresses. With an IOMMU, the address placed in a device descriptor may be an I/O virtual address (IOVA) that the IOMMU translates to selected physical pages. Without an IOMMU, the mapping may use direct addressing or a SWIOTLB bounce buffer. See the DMA API how-to and the current DMA API documentation for the target kernel version.
The address model: never give hardware a CPU pointer
A pointer returned by kmalloc() is a CPU virtual address. It is not automatically a device address, and it is not safe to cast it to one:
device->dma_addr = virt_to_phys(ptr); /* Wrong in general */
device->dma_addr = (dma_addr_t)ptr; /* Wrong */Those shortcuts fail on systems with an IOMMU, on architectures where physical and virtual addressing differ, and whenever the device cannot address the resulting location. The driver must map memory for the specific device and pass the returned DMA address to hardware:
dma_addr_t dma_addr;
dma_addr = dma_map_single(dev, cpu_addr, len, DMA_TO_DEVICE);
if (dma_mapping_error(dev, dma_addr))
return -EIO;
/* Program the device with dma_addr. */
/* Only after device completion: */
dma_unmap_single(dev, dma_addr, len, DMA_TO_DEVICE);A DMA address is the address used by the device. It may be unrelated numerically to the CPU pointer and, with an IOMMU, may not be a physical address at all.
Choose the right buffer strategy
| Requirement | Preferred mechanism | Main trade-off |
|---|---|---|
| One short-lived transfer | Streaming DMA mapping | Requires exact map, completion, sync, and unmap handling |
| Persistent descriptor ring | dma_alloc_coherent() |
May consume expensive or specially managed memory |
| Fragmented or page-based payload | dma_map_sg() |
Requires scatter-gather descriptor handling |
| One allocation shared by devices | dma-buf | Requires attachment, fencing, and lifetime coordination |
| Userspace-created shared allocation | DMA-BUF heaps | Heap names and semantics vary by platform |
| Untrusted device | Restricted IOMMU mappings | Translation and invalidation overhead |
| Device requires physical contiguity | CMA or another suitable contiguous allocator | Allocation pressure and fragmentation |
For ordinary one-shot payloads, normal kernel memory plus a streaming mapping is usually the appropriate starting point. Use an established subsystem allocator when working through networking, block I/O, V4L2, DRM, or another framework that already owns buffer lifetime and synchronization.
Streaming DMA: the normal transfer lifecycle
Streaming mappings are temporary mappings of existing memory for a particular operation. Common APIs include dma_map_single(), dma_map_page(), and dma_map_sg().
- Allocate or obtain the buffer.
- Prepare it on the CPU.
- Map it for the device and the correct direction.
- Check for mapping failure.
- Publish the DMA address to the device.
- Wait for a genuine completion indication.
- Synchronize or unmap the mapping.
- Access the buffer on the CPU only after ownership returns.
- Free or recycle it only after all device references and asynchronous work are gone.
A minimal transmit-style example is:
void *buf;
dma_addr_t dma;
size_t len = PAGE_SIZE;
buf = kmalloc(len, GFP_KERNEL);
if (!buf)
return -ENOMEM;
prepare_payload(buf, len);
dma = dma_map_single(dev, buf, len, DMA_TO_DEVICE);
if (dma_mapping_error(dev, dma)) {
kfree(buf);
return -EIO;
}
submit_to_device(dma, len);
/* Wait for the device's completion mechanism. */
/* Do not overwrite, reuse, or free buf before completion. */
dma_unmap_single(dev, dma, len, DMA_TO_DEVICE);
kfree(buf);An interrupt, completion queue, or device fence must establish that the hardware has stopped using the mapping. A timeout by itself is not proof of quiescence: a wedged device may still issue DMA. A timeout path must reset, isolate, or otherwise prevent further DMA before the buffer is reclaimed.
Use the direction from the device’s perspective
| Device activity | DMA direction |
|---|---|
| The device reads memory | DMA_TO_DEVICE |
| The device writes memory | DMA_FROM_DEVICE |
| The device both reads and writes memory | DMA_BIDIRECTIONAL |
The direction is not merely documentation. It tells the DMA layer what cache maintenance is required and supports debugging. A wrong direction can leave stale CPU cache lines in place or cause later CPU writeback to overwrite data written by the device.
Coherent allocations and their limits
Use dma_alloc_coherent() for structures that remain associated with the device for a long time, such as descriptor rings, or when both CPU and device repeatedly access a stable allocation:
void *cpu_addr;
dma_addr_t dma_handle;
cpu_addr = dma_alloc_coherent(dev, size, &dma_handle, GFP_KERNEL);
if (!cpu_addr)
return -ENOMEM;
/* CPU uses cpu_addr; hardware uses dma_handle. */
dma_free_coherent(dev, size, cpu_addr, dma_handle);“Coherent” means that ordinary cache-maintenance operations are reduced or unnecessary for the allocation’s CPU/device visibility. It does not mean that accesses are mutually exclusive, that writes are ordered for the device protocol, or that the buffer cannot be accessed after free. Memory barriers may still be required before publishing a descriptor or ringing a doorbell.
Coherent memory can also be costly or limited. Do not use it automatically for every large payload. The CPU pointer, DMA handle, device, and size passed to dma_free_coherent() must match the allocation.
If a coherent buffer is mapped into userspace, it must not be freed while that userspace mapping remains valid. The kernel’s infrastructure documentation describes relevant lifetime requirements.
Scatter-gather mappings
Memory that is virtually contiguous is not necessarily physically contiguous. For page-based or fragmented buffers, build a scatterlist and map it with dma_map_sg():
int mapped_nents;
mapped_nents = dma_map_sg(dev, sglist, original_nents,
DMA_FROM_DEVICE);
if (!mapped_nents)
return -EIO;
/* Program hardware using mapped_nents entries. */
/* After completion: */
dma_unmap_sg(dev, sglist, original_nents, DMA_FROM_DEVICE);This count distinction is a frequent source of bugs:
- Use the returned mapped count when programming hardware.
- Use the original count when calling
dma_unmap_sg().
The DMA layer may merge adjacent entries or otherwise transform the list for the device. Treat the mapped list as the device-facing representation.
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A device that supports only 32-bit DMA cannot safely receive an arbitrary 64-bit address. PCI drivers should configure the supported DMA width with dma_set_mask() and, where appropriate, separately configure the coherent allocation mask with dma_set_coherent_mask(). The Linux PCI documentation covers this setup.
Configure the mask before allocating or mapping buffers. A narrow mask can cause the kernel to use a SWIOTLB bounce buffer. That preserves correctness by copying data through an addressable area, but it adds latency, memory bandwidth use, and possible throughput loss.
Mapping can fail because the requested address range is not reachable or because IOMMU, SWIOTLB, or other mapping resources are unavailable. Always check dma_mapping_error() and the return value from dma_map_sg(); never submit an unvalidated address.
Ownership, caches, and ordering
A useful model is to make ownership explicit:
CPU-owned:
CPU may read or write.
Device must not access.
Device-owned:
Device may read or write.
CPU must not access.
Completion:
Device signals completion.
Driver synchronizes and returns ownership to CPU.On a non-coherent architecture:
- Before a device reads CPU-produced data, map or synchronize with
DMA_TO_DEVICE. - Before the CPU reads device-produced data, synchronize with
DMA_FROM_DEVICE. - For bidirectional mappings, synchronize at both handoff points.
Coherency does not replace locking. A coherent buffer can still be corrupted if the CPU updates a descriptor while the device is consuming it.
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Ordering matters as well. The device must not observe a producer index or doorbell before the descriptor and payload are visible. Use the memory barriers required by the device protocol and architecture before making work available. Conversely, do not treat an interrupt as permission to read data until the documented completion and synchronization steps have occurred.
Cache-line sharing
A device-written field should not share a cache line with CPU-written metadata. On a non-coherent system, a later CPU writeback can overwrite the device’s update even though the logical fields appear unrelated. Align and isolate device-written groups, and review the kernel’s DMA grouping annotations such as __dma_from_device_group_begin() and __dma_from_device_group_end() where applicable. See the DMA API cache-line guidance.
IOMMU protection: powerful but not automatic
An IOMMU gives a device a restricted address space. The driver maps only the pages the device should access, and the IOMMU translates the device’s IOVA to those pages. This is especially valuable for untrusted PCIe devices, virtual machines, and pipelines that handle data from different security domains.
An IOMMU cannot correct a driver that maps the wrong pages or maps a buffer larger than intended. A device can still corrupt every byte inside an incorrect or oversized mapping. Isolation also depends on correct domains, permissions, invalidation, and teardown.
Bypass modes can reduce translation overhead while weakening isolation. Strict and lazy invalidation make different performance and revocation trade-offs. These are deployment-specific configuration choices; consult the kernel’s IOMMU parameter documentation rather than assuming one setting is universally correct.
Sharing memory with dma-buf
dma-buf is Linux’s framework for sharing one allocation between drivers, devices, processes, and subsystems through a file descriptor. It is common in graphics, cameras, display pipelines, and video codecs.
The typical workflow is:
- An exporter owns the allocation and creates the dma-buf.
- An importer attaches to it.
- Each device maps the buffer into its own DMA address space.
- Devices coordinate access through implicit or explicit fences.
- CPU access is bracketed by the required begin/end operations.
- The allocation is released only after all users, attachments, and fences are finished.
dma-buf does not automatically make concurrent access safe. If one device is writing while another device or the CPU is reading, the pipeline needs the appropriate fence or synchronization mechanism.
For userspace CPU access, the usual pattern is conceptually:
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DMA_BUF_SYNC_START | read/write flags
access mapped buffer
DMA_BUF_SYNC_END | same read/write flagsDMA_BUF_IOCTL_SYNC addresses CPU cache coherency. It does not wait for another device, lock out another process, or replace device-to-device fences. Applications must wait for relevant work or fences separately.
dma-buf file descriptors should be created with close-on-exec semantics where supported. A descriptor that unintentionally survives exec can grant another program access to the buffer. The dma-buf documentation also describes exporter responsibilities around clearing and readiness.
DMA-BUF heaps
DMA-BUF heaps provide a userspace-visible allocation interface. Depending on the kernel and platform, available heaps may include:
system: virtually contiguous, cacheable system memory.default_cma_region: physically contiguous, cacheable memory backed by a CMA region.- Device-tree-backed shared DMA pools.
system_ccshared memory in certain confidential-computing virtual machines.
Heap availability is platform- and configuration-dependent. Do not assume a heap exists merely because its name appears in documentation. A heap allocation also does not remove the kernel driver’s responsibility to map and synchronize the buffer for each device. See the DMA-BUF heaps documentation.
Userspace buffers and pinned pages
A driver receiving a userspace pointer must not cast it into a device address. It must validate the range, safely manage the pages according to the subsystem’s rules, map them for the specific device, and keep them valid until asynchronous device access has ended.
Long-term page pinning has memory-management and security costs. pin_user_pages() is not a universal recipe: the correct mechanism depends on the subsystem, device write direction, duration, and ownership model. Prefer established subsystem APIs when they already define how userspace buffers are pinned, mapped, synchronized, and released.
Clearing and sanitizing recycled buffers
Correct mappings do not prevent stale-data disclosure. A pooled buffer may still contain bytes from a previous process, VM, device, or security domain. Before exposing it to a new owner, the allocator or exporter must clear it wherever the API contract requires that guarantee.
Distinguish three concepts:
- Initialization: writing known values for program correctness.
- Zeroing: removing residual data before handing memory to a new security domain.
- Sanitization: a broader policy that may also need to address caches, device-local memory, encryption state, or persistent hardware storage.
Zeroing system RAM is not automatically proof that every copy of the data has disappeared from device caches or other platform-specific storage. Define which component owns clearing when buffers are pooled or exported.
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Reset, timeout, hot-unplug, and teardown
The happy path is not enough. A safe teardown sequence generally looks like this:
- Stop accepting new submissions.
- Prevent or quiesce further DMA.
- Drain completions and cancel asynchronous work.
- Wait for or revoke all cross-device fences.
- Detach and unmap shared buffers.
- Unmap streaming mappings.
- Release the final references.
- Free the allocation.
Do not free memory merely because software has stopped waiting. A timed-out device may still hold a DMA address. Reset or isolate the hardware first, and ensure that delayed interrupts, workqueue callbacks, and completion handlers cannot access the buffer after reclamation.
The same principle applies to hot-unplug and fatal errors: the driver must account for outstanding descriptors, IOMMU mappings, userspace mappings, and references held by other importers.
Common failure modes
- Use-after-free DMA: memory is freed or recycled while the device still holds its address. Keep explicit ownership or reference state.
- Wrong direction: cache operations do not match whether the device reads, writes, or does both.
- Missing unmap: IOVA space or mapping resources are exhausted, and stale device access may remain active.
- Unchecked mapping failure: an invalid or zero result is programmed into hardware.
- Descriptor/data reordering: a doorbell or producer index becomes visible before the descriptor or payload.
- Incorrect scatterlist count: the original count is used for hardware instead of the mapped count returned by
dma_map_sg(). - CPU access during device ownership: coherent memory is mistaken for a concurrency mechanism.
- IOMMU assumptions: code depends on translation behavior that is absent or configured differently on another platform.
- Bounce-buffer slowdown: a narrow DMA mask silently adds copying and latency.
- Premature dma-buf reuse: fences are ignored and two users access the allocation concurrently.
- Stale-data exposure: recycled memory crosses a security boundary without clearing.
- File-descriptor leakage: a dma-buf FD survives
execunintentionally.
Code-review checklist
Allocation
- Is the device’s DMA width configured before allocation or mapping?
- Does the hardware require physical contiguity, or can it consume scatter-gather descriptors?
- Is coherent memory reserved for persistent shared structures rather than used indiscriminately?
- Would a subsystem-provided buffer type already solve lifetime and synchronization?
Mapping and handoff
- Is the generic device DMA API used?
- Is the direction expressed from the device’s perspective?
- Are
dma_mapping_error()anddma_map_sg()results checked? - Is the mapped scatterlist count used for hardware and the original count used for unmapping?
- Are CPU writes complete before
DMA_TO_DEVICEhandoff? - Are descriptors published only after their contents are visible, with the required barrier before the doorbell?
Completion and teardown
- Does completion prove that the hardware no longer owns the buffer?
- Are sync or unmap operations performed before CPU reads?
- Is every successful map paired with exactly one matching unmap?
- Do timeout and reset paths prevent delayed DMA before freeing memory?
- Are dma-buf fences, attachments, userspace mappings, and final references drained?
- Is data cleared before the buffer enters a new security domain?
Kernel-version and architecture qualification
DMA attributes, helper behavior, cache rules, and subsystem contracts can vary by kernel version and architecture. The links in this article point to Linux documentation versions that cover the relevant APIs, but driver development should always verify the target kernel tree, architecture, IOMMU configuration, and subsystem rules. Code that appears correct on a cache-coherent x86 system may fail on a non-coherent ARM platform.
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