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Yes—but with an important qualification. In a 2023 study, researchers from Ruhr University Bochum, the Max Planck Institute for Security and Privacy, and collaborators compared scanning-electron-microscope (SEM) images of fabricated chips with trusted design data. They detected 37 of 40 deliberately created design-to-silicon discrepancies across 28 nm, 40 nm, 65 nm and 90 nm CMOS chips. The experiment demonstrated a practical way to look for unauthorized physical changes, not a 92.5% detector for every hardware Trojan and not the discovery of an unknown malicious chip in commercial production.
Why silicon-level inspection matters
A hardware Trojan is an unauthorized change to an integrated circuit. It may stay dormant until a rare trigger, then alter computation, leak information, disable a function or interfere with a larger system. The change can be introduced during design, fabrication or another supply-chain step.
Design houses frequently outsource manufacturing. A trusted RTL or layout can therefore pass normal approval while an untrusted manufacturing path changes the physical implementation. Functional tests may still pass if the Trojan requires an unusual input sequence or operating condition. The Bochum/MPI-SP project asks a different question: does the manufactured structure match the trusted design?
What the 2023 experiment actually showed
The team did not find a previously unknown Trojan in a commercial chip. They manufactured legitimate chips, then changed reference design files after fabrication to create controlled mismatches representing possible Trojan modifications. The physical chips were compared with those altered references to test whether the inspection pipeline could expose unauthorized differences. The institutional account describes the setup as a red-team/blue-team case study; the paper is “Red Team vs. Blue Team: A Real-World Hardware Trojan Detection Case Study Across Four Modern CMOS Technology Generations” (IEEE Symposium on Security and Privacy 2023, DOI 10.1109/SP46215.2023.00044).
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| Process node | Reported result |
|---|---|
| 90 nm | All tested changes detected |
| 65 nm | All tested changes detected |
| 40 nm | All tested changes detected |
| 28 nm | Three subtle changes missed |
Overall, 37/40 is 92.5% of this deliberately constructed test set. It is not the probability of detecting an arbitrary Trojan in the wild. The sample was small, purpose-built and limited to the modifications and layers examined.
How the physical comparison works
- Start with a trusted reference. The investigators use the original layout or other design representation as the expected implementation.
- Prepare the fabricated chip. Chemical and mechanical processing exposes lower metal and device layers for inspection. This is invasive and can destroy the sample.
- Acquire SEM imagery. Thousands of high-resolution images are collected and assembled. One 65 nm example used 4,225 SEM images covering an area containing about 571,000 standard cells.
- Register design and images. Software aligns the design representation with the corresponding physical regions, compensating for scale, rotation and other registration differences.
- Compare cells. Image-processing methods look for standard cells whose observed structures differ from the expected implementation.
- Investigate flags. A flagged cell can reflect tampering, but also dust, hair, contamination, charging, blur, process variation, incomplete layer exposure or alignment error. Human or additional automated triage is required.
“Silicon-level” therefore means inspection of the manufactured physical chip rather than only RTL, netlists, simulation or electrical behavior. It does not mean an instant, non-invasive scan of a packaged device.
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False positives, missed changes and the 28 nm difficulty
The researchers reported approximately 500 false-positive cells among more than 1.5 million examined standard cells. These were cells flagged by the pipeline that were not among the deliberately modified locations. That proportion is useful context, but a real deployment would still need a review process and carefully chosen thresholds.
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The three misses occurred on the 28 nm chip. The researchers noted that a single particle of dust or a hair could obscure a row of cells, while smaller geometries make visual discrimination harder. Better SEM equipment, cleaner preparation, improved registration and machine-learning-assisted classification could help, but those are proposed improvements—not production guarantees.
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What this method can—and cannot—promise
Advantages
- It examines the physical implementation directly rather than waiting for a Trojan to trigger.
- It can operate at standard-cell granularity, potentially exposing additions or substitutions that broad optical inspection would miss.
- It provides a reproducible basis for computer-vision and machine-learning research because the team released imagery, design data and analysis algorithms.
Important limits
- Invasive and slow: sample preparation, SEM acquisition, storage, registration and analysis are costly and unsuitable for checking every mass-produced chip.
- Golden-reference dependence: the design files must be authentic and complete. A compromised reference can make a compromised chip appear to match.
- Coverage gaps: the approach is most effective when a modification changes imaged geometry. Dopant changes, transistor-parameter changes, hidden layers, visually similar cells and attacks exploiting undocumented process behavior may evade it.
- Limited generalization: the study covered 40 controlled discrepancies and process nodes down to 28 nm—not current leading-edge nodes, chiplets, advanced 3D structures, every analog/RF block or every Trojan class.
How it compares with other defenses
Pre-silicon RTL, netlist and formal analysis can find suspicious logic before fabrication, but cannot by themselves prove that an outsourced foundry built exactly that design. Functional tests and ATPG test behavior, not necessarily dormant extra circuitry. Side-channel methods look for unusual power, timing or electromagnetic effects. Optical inspection and conventional failure analysis provide different resolution and coverage. Runtime monitors can detect abnormal operation after deployment.
SEM-to-layout comparison occupies a distinct niche: a high-assurance or forensic check that the physical chip resembles a trusted reference. It is most plausible for high-value devices, foundry qualification, government or defense assurance and sampling-based supply-chain audits—not as a low-cost universal consumer-electronics screen.
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The later “invisible inversion” caveat
A 2026 follow-up, “Hardware Trojans from Invisible Inversions,” shows why visual matching is not proof of trust. Related researchers describe standard-cell implementations that can be functionally different yet visually indistinguishable in SEM images, and present a privilege-escalation backdoor case study in an Ibex RISC-V core. A related artifact points to the public backside-SEM dataset and the DAFT repository; it is follow-up work, not the original 2023 implementation. Its additional via-position analysis reportedly detects the original experiment’s Trojans, including cases missed in the earlier 28 nm data.
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The original paper and preprint are available through IACR ePrint. Ruhr University Bochum says the team released the chip images, design data and analysis algorithms so independent groups can reproduce the benchmark and develop improved registration or classification methods. The university’s summaries provide the headline results and experimental context: CASA/RUB report and RUB announcement.
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Bottom line
The Bochum/MPI-SP work is a meaningful demonstration that SEM images of manufactured silicon can be compared with trusted design data to expose certain Trojan-like physical discrepancies. Its 37-of-40 result is encouraging, especially at 40 nm, 65 nm and 90 nm, but the workflow is invasive, expensive, image-quality-dependent and reference-dependent. Treat it as a promising research and high-assurance inspection technique—not a production-ready proof that a chip contains no hardware Trojan.
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