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OpenOCD is the software bridge between host development tools and embedded hardware. With a compatible debug adapter, transport, target configuration and build, it can provide source-level debugging, in-system flash programming and JTAG boundary-scan testing—not merely breakpoint control.
The OpenOCD User’s Guide defines the project this way: “The Open On-Chip Debugger (OpenOCD) aims to provide debugging, in-system programming and boundary-scan testing for embedded target devices.”
What is OpenOCD used for?
OpenOCD runs as a host-side server. Development tools, commonly GDB, connect to that server; an interface driver then communicates through a physical debug adapter to the target board. Board and target configuration files describe details such as the processor, scan chain, reset behavior and flash memory.
This layered design is why an OpenOCD installation is not automatically compatible with every microcontroller, probe or operation. The adapter driver, transport, target support and configuration must all line up with the installed build.
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- Kind reminder: Our device is designed for experienced embedded engineers or enthusiasts who know how to use it. Please refer to the pictures on this webpage for instructions. We apologize for not providing any additional product user manuals!
Source-level debugging
For supported processors, OpenOCD exposes a GDB-facing debugging path. A debugger can inspect registers and memory, set breakpoints and watchpoints, step through code, and control target execution. Exact processor coverage depends on the OpenOCD version, its drivers and the target configuration.
In-system flash programming
OpenOCD can program supported internal and external flash devices through the debug-support stack. Flash commands and algorithms are target-specific, so “OpenOCD can program flash” does not mean that every chip or memory device is supported. Confirm the exact flash implementation and configuration in the guide and configuration files shipped with your version.
Boundary-scan testing
JTAG can expose boundary-scan capabilities for testing interconnects and device pins. This is a distinct use from CPU debugging and is not available through an SWD-only connection.
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- Compatible With full range of devices: Xilinx FPGAs, XILINX Zynq-7000, XILINX CoolRunnerTM/CoolRunner-II CPLDs, Artix7, SOC, Xilinx Platform Flash ISP configuration PROMs, Select third-party SPI PROMs, Select third-party BPI PROMs, etc. Adaptive target board I/O voltage, support 5V, 3.3V, 2.5V, 1.8V and 1.5V interface levels, VREF levels range from 1.4V to 5V. The measured minimum can support up to 1.2V, and an interface protection circuit is added.
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How the OpenOCD workflow fits together
- Host tools: GDB or another development tool connects to the OpenOCD server.
- OpenOCD server: OpenOCD interprets debugger requests and applies its target and board settings.
- Interface driver: The selected driver talks to the physical debug adapter over the host connection, commonly USB.
- Transport: JTAG, SWD or another supported transport carries signals between the adapter and target.
- Board and target configuration: Configuration files identify wiring, reset behavior, processors, scan chains and flash details.
A simple development board may work with existing interface and board files. Custom wiring, external memory, unusual reset circuitry or a newly supported chip can require board-specific additions, a new target configuration or development work.
See the project’s OpenOCD Project Setup guide for the configuration-file model.
What is the difference between JTAG and SWD?
| Characteristic | JTAG | SWD |
|---|---|---|
| Target scope | Used by supported processors and devices across several ecosystems | ARM-specific debug transport |
| Signals | Uses a multi-signal JTAG interface | Uses fewer signal wires than JTAG |
| Debugging | Supported where the adapter and target configuration provide it | Debug-oriented for supported ARM targets |
| Boundary scan | Supports boundary-scan testing | Does not provide boundary-scan support |
| Selection consequence | Required when boundary scan or JTAG-specific hardware is needed | Useful when the ARM board exposes SWD and only debug/programming functions are required |
JTAG and SWD are therefore not interchangeable choices. Select the transport that the target exposes and that the adapter driver in your installed OpenOCD build supports. The official details are in Debug Adapter Configuration.
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- USB to FPGA Interface: The USB Blaster Download Cable interfaces a USB port on a host computer to an Altera FPGA mounted on a printed circuit board
- Configuration Data Transfer: The cable sends configuration data from the PC to a standard 10-pin header connected to the FPGA
- Versatile Programming Applications: You can use the USB Blaster cable to iteratively download configuration data to a system during prototyping or to program data into the system during production
- Comprehensive Device Support: Supports most of the ALTERA FPGA/CPLD devices, Active Serial Configuration devices, Enhanced Configuration devices, and supports AS, PS, JTAG three download modes
- High-Speed Design Architecture: Features high-speed, stable performance with internal FT245R+CPLD design for efficient programming and debugging operations
Can OpenOCD program flash?
Yes, when the target’s flash technology and OpenOCD support are correctly configured. OpenOCD’s flash support includes specific internal and external memory families and dedicated flash commands, but coverage is not universal.
- Verify that your installed guide documents the target’s processor and flash family.
- Use the target or board configuration that supplies the correct flash geometry and access method.
- Check reset and halt behavior; a target that cannot be placed in the required debug state may fail before programming begins.
- Do not assume that support for one member of a chip family proves support for every related part.
The project’s About OpenOCD and adapter-configuration documentation describe this dependency on debug and target support.
How do I configure OpenOCD for my board?
- Identify the target interface: Determine whether the board exposes JTAG, SWD or another transport, and note the connector pinout.
- Choose the interface configuration: Select the file and driver matching the physical adapter and its host connection.
- Choose a board or target configuration: Start with an existing board file when one accurately describes the processor, reset wiring and flash.
- Check board-specific details: Add settings for non-standard wiring, external memory, voltage translation or reset circuitry when the existing file is incomplete.
- Confirm flash details: Ensure the configuration identifies the correct internal or external flash implementation.
- Run the installed build’s documentation and configurations: Version-specific drivers, target files and commands are authoritative for that installation.
The project organizes common configuration families as interface, board and target files. A configuration that names only a probe is not sufficient if the board’s processor, reset behavior or flash still needs to be described.
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- Category:XILINX FPGA/CPLD configuration and programming Cable
- Software:Xilinx ISE, iMPACT, ChipScope
- Interfaces:JTAG, Slave-Serial and SPI
- Solution:CY7C68013A+XC2C256
- User Guide CD?schematic,software, drivers and examples
What debug probe works with OpenOCD?
No single probe works with every target. OpenOCD’s supported adapter families include CMSIS-DAP and other USB debug adapters, but compatibility depends on the driver present in your build and the electrical connection to the board.
A CMSIS-DAP JTAG/SWD debug probe is a practical category to search for when assembling a setup, not a guarantee of compatibility or a tested product recommendation. Before buying, check:
- Transport support: JTAG, SWD or the protocol your target exposes.
- Target voltage and whether the probe tolerates it or requires level conversion.
- Ground, reset and signal-voltage connections.
- Connector pinout; jumper wires or a pinout-changing cable may be necessary.
- Host-side connection and the corresponding OpenOCD interface driver.
- Whether adaptive clocking is required by the target or wiring.
The official hardware guidance is in Debug Adapter Hardware. A physical adapter alone cannot compensate for an unsupported target or missing configuration.
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Electrical and configuration checks before troubleshooting
- Voltage: Match the probe’s I/O levels to the target; use a suitable voltage-level converter when necessary.
- Pinout: Confirm every signal against the board and probe documentation instead of relying on connector shape.
- Ground: Provide a shared ground between adapter and target.
- Reset: Wire the reset signal when the board or target configuration expects it.
- Clocking: Determine whether the combination needs adaptive clocking or a constrained clock setting.
- Software support: Check the installed OpenOCD guide and configuration directory, not only a generic list of adapters.
What the current version label means
The online OpenOCD User’s Guide currently identifies its documentation as 0.12.0+dev, dated 28 September 2026. That label describes the guide’s documented development version; it is not, by itself, evidence that a stable 0.12.0 release was made. Driver and target support should be verified against the guide and configuration files installed with your particular build.
Choosing an approach by requirement
| Your requirement | What to verify | Likely transport consideration |
|---|---|---|
| Source debugging on an ARM board | Processor support, target file, reset behavior and GDB path | SWD may be sufficient if the board exposes it |
| Debugging plus boundary scan | JTAG-capable target, adapter and configuration | Use JTAG; SWD cannot provide boundary scan |
| In-system programming | Exact flash family, algorithm and memory configuration | Either supported transport may work, depending on target |
| Custom board or external memory | Board-specific configuration and possibly new target support | Transport choice does not remove configuration work |
OpenOCD is best understood as an extensible hardware-access layer rather than a universal programmer. Its value comes from connecting the right host tools, adapter, transport and target description for a particular embedded design.
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