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Onsemi licensed Weebit Nano’s ReRAM intellectual property for its Treo Analog and Mixed-Signal Platform on January 1, 2025. The agreement is intended to add embedded non-volatile memory to onsemi’s 65-nm Bipolar-CMOS-DMOS (BCD) technology. It was an important integration and business-development milestone—not the launch of a finished Treo product containing Weebit memory.
Later in 2025, Weebit reported that test chips using its embedded ReRAM had been taped out at onsemi’s East Fishkill, New York, production fab. That strengthens the evidence that integration progressed, but tape-out still falls short of qualification, volume production, or publicly identified commercial availability.
What was announced?
Weebit Nano announced a license agreement with onsemi to integrate its ReRAM technology into the Treo platform. The agreement’s commercial terms were not publicly disclosed. Weebit’s announcement described the target as onsemi’s Treo Analog and Mixed-Signal Platform and characterized the memory as a low-power, high-temperature embedded-NVM option.
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The announcement date was January 1, 2025. The EE Times coverage published on February 7, 2025, provided additional technical and commercial context. It did not announce a shipping product, a foundry service, or a mass-production program.
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What is Treo?
Treo is a technology platform, not one individual chip. Onsemi describes it as a modular analog and mixed-signal platform built on 65-nm BCD technology. BCD combines:
- Bipolar devices for precision analog functions.
- CMOS for digital control and processing.
- DMOS for higher-voltage and power functions.
The platform is designed around reusable analog, digital, sensing, communications, and power blocks. Onsemi’s platform materials cite a voltage range from 1 V to 90 V and operating temperatures up to 175°C. They also identify the company’s 300-mm East Fishkill, New York, fab as a manufacturing site.
Onsemi has positioned Treo for automotive, industrial, medical, communications, and AI-data-center power applications. Associated product families include voltage translators, ultra-low-power analog front ends, LDOs, ultrasonic-sensor interfaces, multiphase controllers, and single-pair Ethernet controllers. These are platform-level capabilities; they are not specifications of the Weebit ReRAM block itself. See the Treo platform overview and onsemi’s platform announcement.
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ReRAM, also called RRAM, stores data by changing the resistance of a memory cell. Weebit supplies licensable embedded-memory IP rather than a standalone memory chip. If integrated into a Treo device, the memory would sit on the same die as the analog, digital, sensing, communications, or power circuitry.
That embedded NVM could store:
- Firmware or boot code.
- Calibration constants and manufacturing trim data.
- Configuration settings.
- Device-specific control parameters.
- Small amounts of data that must survive power removal.
For a power-management or sensor IC, this can reduce dependence on an external EEPROM, flash chip, or controller. The potential system benefits include fewer components, less board space, fewer pins, and simpler product integration. ReRAM in this context is not intended to replace the large-capacity storage used in phones, computers, or data-center systems.
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Why add memory to a 65-nm BCD process?
Treo targets chips that combine precision analog, digital logic, high-voltage power handling, sensors, and communications interfaces. Those devices often need at least modest non-volatile storage for calibration, configuration, firmware, security settings, or production data.
Without suitable embedded NVM, a designer may need to add an external memory component, use a separate controller, or move to a process with embedded flash. Each choice can affect cost, board area, power consumption, pin count, software, testing, and qualification.
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Why ReRAM instead of embedded flash?
According to comments reported by EE Times, Weebit argues that ReRAM can be integrated as a back-end technology, potentially reducing disruption to front-end analog and power devices. The company also contrasted approximately 3 V programming for its ReRAM implementation with approximately 12 V for flash.
That voltage comparison is a vendor-supplied comparison, not a universal rule for every ReRAM and flash implementation. Embedded flash may require specialized process steps and higher-voltage programming circuitry, which can be costly or difficult to add to mature high-voltage BCD processes.
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ReRAM may offer a lower-power integration route, but it is not categorically better than flash. The practical choice depends on density, endurance, retention, read and write speed, error correction, die area, process compatibility, qualification data, software support, and unit cost.
Why not MRAM?
Weebit told EE Times that MRAM can be more economically attractive at advanced digital nodes but less attractive for the particular older, high-voltage BCD use case targeted by Treo. The company cited the additional materials, equipment, and process complexity that may be involved.
That is Weebit’s assessment, not an independent cost study or a claim that MRAM cannot be used with BCD. MRAM’s suitability depends on the specific process, density, reliability requirements, and production economics.
ReRAM compared with the alternatives
| Option | Potential advantage | Key question for Treo-class devices |
|---|---|---|
| Embedded ReRAM | May add modest-capacity NVM to a mature mixed-signal process with limited process disruption. | Can retention, endurance, area, yield, and qualification meet the exact automotive or industrial requirement? |
| Embedded flash | Established ecosystem and potentially useful density. | Are the extra process steps and programming-voltage requirements economical in 65-nm BCD? |
| MRAM | Strong endurance and fast operation in suitable processes. | Is its materials and integration cost justified for this high-voltage mixed-signal platform? |
| External EEPROM or flash | Widely available and easy to select by capacity. | Are the additional component, pins, board area, power, and software complexity acceptable? |
Public information does not specify the Treo/ReRAM macro’s density, read and write performance, die-area overhead, error-correction design, retention at Treo temperatures, or endurance under the final operating conditions.
Potential applications
The combination could be relevant to Treo-based devices such as automotive sensor and power ICs, industrial controllers, medical analog front ends, communications interfaces, and power-management devices for AI data centers. Possible functions include storing calibration data in a sensor interface, configuration values in a power controller, or local firmware in a communications IC.
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Those are plausible use cases based on Treo’s stated application areas. They do not prove that every Treo product will contain Weebit ReRAM, and no specific commercial part was identified in the cited public material as shipping with the technology.
Milestone timeline
- November 11, 2024: Onsemi announced the Treo analog and mixed-signal platform.
- January 1, 2025: Weebit announced its ReRAM license agreement with onsemi.
- February 7, 2025: EE Times published analysis and interviews explaining the technical rationale.
- April 30, 2025: Weebit reported further commercial and qualification progress, including a claim of ReRAM qualification at 150°C and 100,000 cycles.
- Later in 2025: Weebit reported tape-out of test chips featuring its embedded ReRAM at onsemi’s East Fishkill production fab.
The later milestone is significant because it indicates that the technology moved beyond a purely prospective licensing announcement. However, the reported 150°C and 100,000-cycle result concerns Weebit’s stated qualification work and should not be treated as proof that every future Treo/ReRAM product has completed full automotive qualification.
Independent reader supportYour contribution helps us test, update, and keep practical guides available for everyone.What tape-out proves—and what it does not
A tape-out means a design has been released for manufacturing. It can demonstrate that design and process-integration work has reached a manufacturing stage, but it does not by itself prove that the resulting wafers work or that the memory meets its targets.
Tape-out does not establish:
- Functional silicon.
- Final endurance or data-retention performance.
- Automotive qualification of a production device.
- Volume manufacturing.
- Customer availability.
- Commercially favorable die-area or unit economics.
Weebit described the reported chips as test vehicles for testing and qualification ahead of anticipated volume production. “Anticipated” is not the same as confirmed production, and no first commercial product number or volume-shipment date was established by the February 2025 coverage.
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What the agreement means commercially
Weebit described onsemi as a tier-one semiconductor supplier and the agreement as a major commercial milestone. Onsemi’s IDM structure matters because it controls both product development and manufacturing, potentially giving a successful memory integration a path into multiple product families.
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Weebit has described a business model involving licensing revenue, non-recurring engineering fees, milestones, and production-volume royalties. The specific economics of the onsemi agreement—including any license fee, royalty rate, minimum commitment, or production schedule—remain confidential in the cited public sources.
For onsemi, the attraction is the possibility of giving future Treo products local NVM without adding a separate memory component. For Weebit, the agreement provides a route to demonstrate its IP inside a major IDM’s high-voltage mixed-signal ecosystem.
What this does not mean
- It does not mean a finished product launched in February 2025. The original announcement concerned licensing and integration.
- It does not mean every Treo product uses Weebit ReRAM. Onsemi’s statement that Treo-based products are sampling or in production does not identify which products contain this memory.
- It does not mean ReRAM replaces external flash in every system. The likely role is modest-capacity embedded storage.
- It does not mean Treo’s 175°C platform figure applies automatically to the memory. Memory operation, endurance, and retention require separate evidence.
- It does not mean tape-out equals production. Characterization, reliability testing, qualification, and product release still matter.
What remains unknown
- The ReRAM macro’s density and die-area overhead in Treo.
- Read, write, and programming performance.
- Retention and endurance at the final operating voltage and temperature.
- Error-correction and security features.
- Qualification status of a Treo-integrated production product.
- The first commercial product to include the memory.
- Volume-production timing and customer availability.
- License value, royalty rates, and minimum commitments.
Bottom line
Onsemi’s Treo–Weebit agreement is a credible semiconductor-integration milestone: it aims to put embedded ReRAM into a 65-nm BCD platform that combines analog, digital, sensing, communications, and power functions. The later test-chip tape-out provides evidence of progress beyond the initial announcement.
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1Clear out junk files and repair common Windows errors2Fix the driver behind crashes, sound loss and screen glitches3Repair Windows errors before they cause bigger problemsThe most accurate description, however, is a path toward embedded NVM in future Treo products—not proof that a mass-produced, publicly identified ReRAM-equipped Treo device was already available in February 2025. The decisive evidence will be a qualified production part with published memory specifications, a product number, and confirmed volume shipments.
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