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The NCO/DDS: A Periodic Waveform Generator is an older VHDL DSP core listed on OpenCores and All About Circuits. Its published specification describes a 32-bit phase accumulator and simultaneous 12-bit signed sine, cosine, square, and sawtooth outputs. It may suit learning, prototyping, or a design that can validate and accept its GPL license; the listing alone does not establish current maintenance or guarantee its historical timing and signal-quality figures on a modern FPGA.
What the core does
NCO means numerically controlled oscillator; DDS means direct digital synthesizer. In this application the terms describe essentially the same digital frequency-generation method. A reference clock advances a phase accumulator, and the accumulated phase is converted into waveform amplitude samples. Those samples can feed downstream DSP logic or a digital-to-analog converter (DAC). The core itself produces digital values, not an analog oscillator output.
The OpenCores project description advertises four outputs at once: sine, cosine, square, and sawtooth (ramp). Sine and cosine are useful for quadrature processing, mixing, modulation, demodulation, and complex test signals. Square and ramp outputs can be useful for digital stimulus or control. The listing describes simultaneous outputs, not simply a selector that emits one chosen waveform. See the OpenCores project overview and All About Circuits listing.
Published specifications for the original listing
| Property | Published value |
|---|---|
| Implementation and category | VHDL; DSP core |
| License and status | GPL; listed as stable and FPGA-proven |
| Bus interface | Not Wishbone-compliant |
| Phase accumulator | 32 bits |
| Output samples | 12-bit signed |
| Frequency resolution | Fs / 2^32 |
| Phase resolution | 2π / 2^12, as stated in the listing |
| Outputs | SIN, COS, SQUARE, SAWTOOTH |
| Published signal-quality figures | Approximately 70 dB SNR and 70 dB SFDR |
| Latency | 2 clock cycles |
| Historical speed claim | 500 MHz or better on cited Xilinx Virtex-5 and Altera Stratix III examples |
These are catalog-level figures for the original OpenCores/AAC entry, not guarantees for every configuration or target. The 500 MHz claim is tied to old device examples, not a universal maximum frequency. Actual timing depends on the RTL revision, configuration, FPGA, constraints, synthesis and implementation tools, and integration. The approximate SNR and SFDR figures likewise lack enough conditions in the listing to treat them as a directly comparable, universal performance guarantee.
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How to calculate the output frequency
For an N-bit phase accumulator, the basic DDS tuning relationship is:
f_out = phase_increment × Fs / 2^N
Here, Fs is the clock rate at which phase advances, phase_increment is the tuning word, and N is accumulator width. For this listed core, N = 32, so the ideal frequency step is Fs / 2^32. To choose a tuning word for a requested frequency:
phase_increment = round(f_out × 2^32 / Fs)
For example, at a 100 MHz sample clock and a 1.7 MHz target, the calculated tuning word is approximately 73,014,444. This is a calculation from the published accumulator width, not a value verified as a documented core interface setting. The listing uses the 1.7 MHz at 100 MHz example. At 100 MHz, one tuning-word step corresponds to about 0.0233 Hz.
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Rounding the ideal tuning word introduces a small frequency error. In general:
error = (actual_phase_increment − ideal_phase_increment) × Fs / 2^32
The accumulator can encode tuning words that make the sampled waveform alias. For a real-valued output, the useful unaliased range is generally below the Nyquist frequency, Fs / 2. A fine theoretical tuning step does not mean the output frequency is accurate to that step in a finished system: reference-clock accuracy and jitter, implementation effects, and measurement conditions also matter.
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Three different kinds of resolution
The listing’s 32-bit accumulator, 12-bit phase-resolution notation, and 12-bit signed output describe different parts of the design:
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- Accumulator width sets the granularity of frequency tuning. A 32-bit phase accumulator can offer very small frequency steps.
- Phase-to-amplitude resolution concerns how phase is translated into a waveform value. The listing gives
2π / 2^12; this should not be mistaken for 32-bit amplitude precision. - Output width governs the available amplitude quantization. The original listing specifies 12-bit signed samples.
These parameters alone do not determine spectral purity. Phase truncation, lookup-table structure, amplitude quantization, optional dithering, clock quality, DAC behavior, and output filtering can all affect spurs and noise. The listed approximately 70 dB figures should not be inferred from the accumulator width, nor compared with another product’s figures without matching measurement conditions.
Obtaining and integrating the core
The OpenCores project page is the appropriate place to check project navigation and download availability; the AAC entry also shows a download link. Do not assume that a link works today or that a package, its documentation, and the catalog summary all refer to the same revision. The listing dates the project to October 22, 2008, and reports an update on January 27, 2020. It describes the basic version as complete and tested and mentions possible future SNR/SFDR optimization, but those details do not establish active maintenance in 2026.
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- Bandwidth: 100MHz
- Attenuation: x1/x10
- System input resistance,10M / 1M, typical input capacity 85-115pf / 18.5-22.5PF
- Max. Voltage: x1: <200V DC + peak AC, x10: <600V DC + peak AC
- Compensation range 15-40 PF, tip/head style: 5 mm
Before wiring the block into a design, inspect the actual top-level VHDL and matching documentation. The catalog summary does not provide a complete port specification, so it is not enough to establish port names, reset polarity or synchronization, enable behavior, tuning-word update timing, optional phase control, or output-valid signaling. Check whether outputs are registered, whether all four are active together, and whether the implementation infers memories or relies on vendor-specific primitives. Interpret the samples as signed values unless the RTL documentation says otherwise.
- Obtain the RTL and documentation for the same revision, then inspect the top-level entity, generics, ports, and reset requirements.
- Add the VHDL to the FPGA project, define the reference/sample clock, and apply timing constraints for the actual target.
- Calculate the tuning word with the 32-bit formula. Drive it and any enable or phase control according to the revision’s documented update rules.
- Simulate reset, startup, frequency changes, and enough cycles to observe several output periods. Check that measured latency matches the published two-cycle claim.
- Check waveform shape, signed scaling, sawtooth wraparound, square-wave behavior, and sine/cosine alignment. Do not assume the sign of the quadrature phase relationship without verifying it.
- Synthesize for the target and review resource use and timing reports. Validate frequency and, if important, spectral purity in simulation or hardware.
- For a DAC, add suitable scaling and interface logic, handle clock-domain requirements, and account for reconstruction filtering. Square and sawtooth signals contain harmonics and generally need more filtering than a sine wave.
License and suitability
The AAC/OpenCores listing identifies the core as GPL. Source availability is not the same as a permissive BSD- or MIT-style hardware license, and “open source” does not settle whether a particular proprietary product or distribution model is compatible. Review the exact license text included with the version you obtain, including its version and terms for modification, redistribution, and derivative designs. For a commercial product, have the project’s legal team assess the intended use; this is not legal advice.
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The original core is worth considering when an inspectable VHDL reference design, four basic simultaneous waveforms, and portability are more important than current vendor integration—and when its license and validation burden are acceptable. It is a weaker choice when the project needs an actively maintained release, a standard streaming interface such as AXI4-Stream or Avalon-ST, guaranteed support, documented current-device performance, high SFDR, or licensing certainty. The “no Wishbone” listing also means it should not be assumed to provide a ready-made bus interface.
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- Package: 1 x BNC to double-headed alligator clip test line; 1 x BNC to double-head test hook test line; 1 x BNC to double-stack test line; 1 x Double-headed BNC coaxial line.
- Used with Oscilloscopes from All Manufacturers , Equipped with The Standard BNC Connector.
Do not confuse the listing with the current ZIPcores DDS
ZIPcores publishes a commercial DDS datasheet with a similar four-waveform description, but it has a materially different published specification set. Treat it as a separate product or revision unless package history or vendor confirmation establishes continuity; do not transfer its specifications to the older GPL OpenCores listing.
| Item | OpenCores/AAC listing | ZIPcores commercial DDS datasheet |
|---|---|---|
| Output width | 12-bit signed | 16-bit signed |
| Accumulator | 32-bit | 32-bit |
| Additional feature stated | Not established by the summary | Optional phase dithering and 32-bit phase shift |
| Published quality figures | Approximately 70 dB SNR and SFDR | Approximately 100 dB SNR; better than 110 dB SFDR with dithering |
| Speed claim | 500 MHz or better on historical Virtex-5/Stratix III examples | 350 MHz-plus benchmark stated in commercial material |
| License model | GPL, according to the listing | Commercial |
These figures are not directly comparable without equivalent test setups. The ZIPcores datasheet describes an interface with clk, active-low asynchronous reset, active-high en, 32-bit phase_inc and phase_shift, and 16-bit signed waveform outputs. Those interface details belong to that datasheet; they should not be assumed to describe the older OpenCores source. The ZIPcores product page has listed a $3,000 price, but pricing can change: request a current quote, confirm supported devices and revision, and ask what evaluation RTL is available before purchasing.
Alternatives by design environment
- AMD DDS Compiler: A natural option for AMD FPGA projects using Vivado when vendor integration, device support, and current implementation documentation matter. AMD says it is included with the Vivado Design Suite under its applicable end-user license. It is less suitable if the design must stay independent of the AMD toolchain. See the AMD product page, product guide, and Vivado 2026.1 performance and resource data.
- Intel FPGA NCO IP: A practical choice for Intel FPGA designs built in Quartus Prime, where IP Catalog integration and Intel device documentation are useful. Review the NCO IP guide and Intel IP evaluation and licensing information; evaluation capabilities and full-use licensing are distinct.
- OpenCores DDS Synthesizer: A separate project, not another name for this waveform generator. Its overview describes a sine output with runtime frequency and phase adjustment, a quarter-wave lookup table, and a pipelined architecture. Verify its source against your needs, especially if simultaneous square, ramp, and quadrature outputs are required. See the project page.
- Custom RTL: A team can build a phase accumulator, quarter-wave table and symmetry logic, optional dithering, registered output, and a project-specific streaming wrapper. That offers control over interfaces and architecture but makes verification, timing closure, documentation, and maintenance the team’s responsibility.
- Commercial ZIPcores DDS: Consider it when commercial licensing, vendor engagement, and the higher published signal-quality targets are relevant. Obtain a current quote and verify the exact deliverables and performance conditions rather than treating its datasheet as a specification for the GPL core.
Bottom line
The original OpenCores/AAC waveform generator is a useful, compact VHDL NCO/DDS reference: its listed 32-bit accumulator gives fine theoretical frequency tuning, while its outputs are 12-bit signed samples and its catalog reports two cycles of latency. Its age, GPL license, incomplete interface summary, and historical performance claims make source inspection and target-specific verification essential. Choose it when those trade-offs fit; choose vendor IP for a supported, tool-integrated flow or commercial IP when the required license, support, and documented performance justify it.
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