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MosChip says it has completed silicon bring-up and delivered packaged, tested silicon for a custom 28-nm system-on-chip (SoC) developed for ISRO’s Space Applications Centre (SAC) and India’s satellite-navigation program. The January 19, 2026 announcement marks a significant engineering delivery—but it does not establish that the chip is flight-qualified, in mass production, or already deployed in a satellite.
What MosChip delivered
In a January 19, 2026 filing to the stock exchanges, MosChip said it had completed silicon bring-up and delivered packaged silicon for SAC’s custom SoC. The company described the project as part of India’s satellite-navigation program and said the parts were functionally validated against specification and handed to SAC for the next stage of productization.
That wording matters. Tape-out is the point at which a design is sent to a foundry for fabrication. Silicon bring-up follows fabrication: engineers power up returned chips, check that key functions operate, and investigate problems. Packaged silicon delivery means assembled parts were supplied, rather than only design files or a wafer-level result. These are meaningful steps beyond design completion, but they do not by themselves mean the chip has passed mission qualification or entered volume production.
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MosChip says its work covered the implementation and delivery path from netlist to packaged silicon. The filing lists design-for-test (DFT) architecture, DFT implementation and verification, full-chip physical design and signoff, redistribution-layer (RDL) design and routing, package design, tester-board design, and post-silicon validation.
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- Prepare the design for testing: DFT techniques add structures that help test a chip during manufacturing and after fabrication.
- Implement and sign off the physical design: The logical design is laid out for fabrication and checked against relevant design constraints.
- Design interconnect and packaging: MosChip reports RDL work and a 10-layer flip-chip ball-grid-array (FC-CBGA) package. In this package format, the die is connected to the package through flip-chip connections, with an array of solder balls providing external connections.
- Assemble and test engineering samples: The company says the samples were validated on automated test equipment (ATE), which applies test patterns and measures device behaviour.
- Bring up and validate the silicon: MosChip reports that the packaged parts were shown to function against specification before delivery to SAC.
The filing presents this scope as a turnkey execution effort. It does not specify who developed the original SoC architecture or supplied its RTL and IP, whether MosChip was responsible for the entire chip design, or who owns the resulting intellectual property. The safest description is that MosChip delivered the listed implementation, packaging, test and validation work—not that it independently originated every part of the SoC.
Why SAC and satellite navigation matter
The customer named in the announcement is ISRO’s Space Applications Centre, based in Ahmedabad. SAC works on space-borne and airborne instruments and applications, including communications, navigation and remote sensing, and supports payload development and related testing. It is not ISRO headquarters or the Satish Dhawan Space Centre launch site.
MosChip identifies the SoC’s program as India’s satellite-navigation effort. ISRO describes navigation payloads as part of its work, and NavIC as India’s regional satellite-navigation system, intended to provide positioning services over India and a surrounding region. The public MosChip announcement does not name a particular NavIC satellite, receiver, payload or mission for this chip, so it should not be described as already installed in any of them.
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There is related ISRO context, but not a confirmed identification. ISRO’s 2025 achievements material says an indigenous baseband ASIC supporting NavIC and other GNSS signals was realized on 28 nm for civilian and strategic platforms. That page does not name MosChip or explicitly say that its ASIC is the device MosChip delivered. The two announcements are consistent with a broader effort to develop navigation silicon, but the available public information does not prove they refer to the same chip.
ISRO’s 2025 research-area material also describes a 28-nm NavIC/GNSS baseband ASIC concept with roughly 50 million NAND2-equivalent gates and up to 100 tracking channels. Those are details of the architecture described in that material; MosChip has not publicly identified its delivered SoC as that design or confirmed that it has those specifications.
What 28 nm tells you—and what it doesn’t
“28 nm” identifies the semiconductor manufacturing process node used for the implementation. It is not a direct specification for clock speed, power consumption, die size, navigation accuracy, radiation tolerance or overall quality. Nor does a process-node label establish that a chip is suitable for spaceflight.
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Twenty-eight nanometres is a mature process rather than the leading edge of semiconductor manufacturing. A mature node can be a practical choice when design experience, availability and project requirements matter more than using the newest process. Whether it is the right choice for a particular navigation chip depends on its design and system requirements, which have not been disclosed here.
MosChip’s silicon-engineering services page identifies the project as implemented on TSMC 28 nm. This supports saying that the project used TSMC’s 28-nm process. It does not show that wafer fabrication, packaging, assembly or all testing took place in India.
An Indian engineering milestone, not proof of domestic fabrication
The announcement is evidence of Indian semiconductor engineering work spanning implementation, packaging coordination, testing and silicon validation for a strategic program. But those activities are different from wafer fabrication. MosChip identifies itself as a fabless semiconductor and engineering company, and its services page names TSMC 28 nm for this project. The public materials do not establish where wafers were fabricated, where packaging and assembly occurred, or whether all test infrastructure was domestic.
Accordingly, the supported claim is that an Indian company completed substantial turnkey ASIC execution for an ISRO centre. The announcement does not support calling the chip fully manufactured in India or claiming it is India’s first domestically fabricated space chip.
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MosChip says delivery enables SAC to move to productization. That describes a next development stage, not a confirmed production schedule. Depending on the intended use, further work could include system integration, reliability and environmental evaluation, and mission-specific qualification. A packaged engineering sample that passes ATE checks is not automatically qualified for launch.
The filing provides no radiation-hardening method or radiation-test results, nor results for vibration, temperature cycling or thermal-vacuum testing. It also does not name a qualification standard or target mission. Without that information, there is no basis to call the chip radiation-hardened, flight-qualified or flight-proven.
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ASICs can, depending on the design and production scale, offer advantages in size, power or per-unit cost over a programmable FPGA. The trade-off is that an ASIC is less flexible after fabrication and generally requires substantial up-front design and fabrication investment. Whether those trade-offs apply favorably to this particular SoC cannot be assessed without its specifications, costs and production plans.
What the announcement leaves undisclosed
MosChip’s filing confirms a delivery milestone but gives little detail about the chip’s capabilities or commercial scale. It does not disclose the SoC’s name, CPU or DSP architecture, core count, clock frequency, die area, power use, supported navigation signals or bands, tracking-channel count, or positioning performance. Nor does it provide production quantities, a delivery schedule for production units, contract value, expected revenue or a follow-on order.
Those unknowns limit what can be inferred about technical performance and business impact. MosChip’s description of the program as a turnkey, single-owner effort is the company’s account of its service model; its CEO’s characterization of first-pass silicon success is likewise management’s claim, not an independently audited result.
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Why the milestone is still significant
Moving a custom ASIC from implementation through package, test and silicon bring-up is a more substantial accomplishment than delivering a design database alone. It shows that MosChip completed a complicated engineering handoff for a navigation-related program and supplied functional packaged silicon to SAC. That can help reduce coordination risk between design implementation, packaging and test.
The larger strategic significance is plausible but should not be overstated. Indigenous design and engineering can strengthen control over critical electronics supply chains, while the use of a named external foundry shows why “Indian chip capability” does not automatically mean every manufacturing stage is domestic. The next evidence to watch for would be a disclosed qualification or integration result, a production decision, or a mission-linked announcement—not just the completion of bring-up.
Sources: MosChip stock-exchange filing; MosChip silicon-engineering services; ISRO’s SAC profile, payloads overview, 2025 achievements and 2025 research-area document.
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