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On October 4, 2019, Micron announced that it had taped out its first fourth-generation 3D NAND design using a replacement-gate architecture, with up to 128 active layers and CMOS-under-the-array integration. Micron also reported first yielding dies and expected commercial production during calendar 2020—but initially only for selected products. The milestone was technically important, yet it was not a retail SSD launch or an immediate company-wide cost breakthrough.
What Micron actually announced
Micron’s announcement concerned a manufacturing and process-development milestone. The company had completed the first tape-out of its fourth-generation 3D NAND using replacement gate, abbreviated RG, and had produced yielding dies. The design supported up to 128 active memory layers while retaining Micron’s CMOS-under-the-array approach.
In semiconductor manufacturing, a tape-out means that the design data needed to create production masks has been released for fabrication. It is a significant step beyond a concept or laboratory demonstration, but it does not mean that the process has reached mature, high-volume production. Yielding dies show that the design produced functional results; they do not establish final yield, cost, endurance, throughput, or customer availability.
Micron said the technology was expected to enter commercial production in calendar 2020. However, the first RG process was intended for a selected group of products rather than the company’s entire NAND portfolio.
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AnandTech’s contemporaneous report therefore described an emerging process technology, not a universally available 128-layer NAND product.
What “up to 128 layers” means
In 3D NAND, memory cells are built vertically in a stack rather than placed only across a two-dimensional surface. Increasing the number of active wordline layers can increase the number of cells—and therefore the amount of storage—on a die without requiring a proportional increase in its footprint.
“Up to 128 active layers” should not be read as saying that every die or product would use exactly 128 layers. Layer count is also not the same thing as total die capacity. Package organization, cell mode, peripheral circuitry, redundancy, and the final product design all affect usable density.
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1Repair Windows errors before they cause bigger problems2Fix the driver behind crashes, sound loss and screen glitches3Clear out junk files and repair common Windows errorsNor does a 128-layer NAND die automatically make a 128-layer SSD. An SSD combines NAND packages with a controller, firmware, interface, power-management components, and sometimes DRAM or other buffering. The NAND process is one component of the finished product.
Replacement gate: why the process mattered
Replacement gate is a gate-formation architecture used in the construction of the NAND stack. At a high level, a temporary or sacrificial stack is formed first; portions of that structure are subsequently replaced with the final conductive gate or wordline material. The exact materials, etch sequence, deposition sequence, and cell structure used by Micron were not disclosed in the supplied 2019 report, so more specific process claims would go beyond the evidence.
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Micron’s move was significant because it represented a departure from the floating-gate technology that Micron and Intel had used for years. The reported objectives of the RG design included:
- smaller die size;
- lower manufacturing cost over time;
- potential performance improvements; and
- an easier path to later process generations.
These were intended or expected advantages, not measurements published with the announcement. The report supplied no figures for latency, endurance, write speed, wafer cost, die-area reduction, yield, or cost per bit. It is therefore accurate to say that replacement gate was designed to improve those areas—not that the tape-out proved a specific improvement in each one.
CMOS under the array is a separate idea
CMOS-under-the-array, often called CuA, describes where the NAND peripheral circuitry is placed. Instead of occupying lateral space beside the memory array, much of the CMOS circuitry is positioned beneath it. This can improve array utilization and potentially reduce the die footprint.
CuA and replacement gate address different problems:
| Technology | What it describes | Primary purpose |
|---|---|---|
| Replacement gate | A gate or wordline formation architecture | Improve scaling, integration, and potentially cost and performance |
| CMOS under the array | Placement of peripheral CMOS beneath the memory array | Use die area more efficiently |
Micron used both approaches in this generation, but they should not be treated as interchangeable names for the same feature. The report did not quantify the area advantage of CMOS-under-the-array or provide a detailed layout comparison.
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Why 128 layers did not immediately cut Micron’s NAND costs
The most important business detail was that the first RG implementation would not be deployed across all product lines. Micron was still ramping its 96-layer 3D NAND, which was expected to supply the vast majority of its products during the following year.
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That created a staged transition:
- The existing 96-layer process continued ramping into broad production.
- The 128-layer RG design taped out and produced yielding dies.
- The first RG products entered production selectively.
- A later RG generation was expected to spread more broadly and deliver the larger economic benefit.
Micron expected minimal NAND cost reduction in fiscal 2020. It anticipated more meaningful reductions in fiscal 2021, after a second-generation RG node was broadly deployed.
This distinction matters because several different kinds of improvement are easily confused:
- Technology density: the number of active layers or the amount of memory that can fit on a die.
- Per-product cost: the economics of products that actually use the new process.
- Company-wide cost: the average cost across all NAND shipped, including products still made on older nodes.
- Mature-node economics: the cost after yield, qualification, tooling, process learning, and volume have improved.
A denser design can eventually reduce cost per bit, but a new process may initially carry extra integration, qualification, and yield costs. If only a small portion of shipments uses it, the company-wide effect remains limited even when the underlying technology is promising.
Why selective deployment can make sense
Introducing a new NAND process selectively allows a manufacturer to manage technical and financial risk. Higher-value products may justify the expense of a new process before it is economical for every commodity application. Selective deployment also gives the manufacturer time to improve yield and qualify the design with customers while continuing to ship mature NAND from the preceding generation.
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- 300% faster than a typical hard drive
- Improves battery life because it’s 45x more energy efficient than a typical hard drive
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- Crucial 3-year limited warranty
AnandTech suggested that the first RG node could be tailored toward higher-average-selling-price applications such as mobile and consumer products. That was an inference from the deployment strategy, not a disclosed list of products. The 2019 report did not identify particular SSD models, smartphone customers, controllers, package types, densities, or qualification dates.
Independent reader supportYour contribution helps us test, update, and keep practical guides available for everyone.The Micron–Intel context
Micron and Intel had a long history of NAND-development cooperation, and both companies had used floating-gate technology in earlier generations. Against that background, the RG announcement raised an obvious question about whether the new process was a joint development.
According to the AnandTech report, Micron said the replacement-gate technology had been developed solely by Micron without Intel input. That statement should be understood narrowly. It distinguishes this reported RG development from the companies’ earlier relationship; it does not establish that every piece of surrounding NAND knowledge, intellectual property, or prior process technology was unrelated to Intel.
What the announcement proved—and what it did not
It established
- Micron had taped out a fourth-generation 3D NAND design.
- The design used replacement gate and CMOS under the array.
- The design supported up to 128 active layers.
- Micron had obtained first yielding dies.
- A calendar-2020 production path was planned.
It did not establish
- broad availability of 128-layer NAND;
- mature high-volume manufacturing yield;
- a specific SSD launch;
- measured performance or endurance improvements;
- a measured cost-per-bit reduction; or
- competitive superiority over other NAND manufacturers.
It also did not prove that retail SSD prices would fall. The cost discussion concerned Micron’s NAND manufacturing outlook, and Micron specifically expected little company-wide cost reduction in fiscal 2020.
Timeline
| Date or period | Milestone |
|---|---|
| October 4, 2019 | Micron announced the tape-out and first yielding dies for its replacement-gate 3D NAND. |
| 2019–2020 | Micron was ramping 96-layer NAND while planning initial, selective RG production. |
| Fiscal 2020 | Micron expected minimal company-wide NAND cost reductions from the first RG node. |
| Fiscal 2021 | Micron expected more meaningful savings after broader deployment of a second-generation RG node. |
The fiscal-year language reflects Micron’s 2019 guidance and should not be read as current guidance. The original announcement is now a historical account of a process transition; claims about what actually shipped or how the economics later developed require separate evidence.
The significance of the milestone
Micron’s 2019 tape-out marked an inflection point in its NAND process strategy. The headline number—128 layers—was important, but the broader story was the combination of vertical scaling, replacement-gate integration, and CMOS-under-the-array design.
Technically, the company had moved the RG design from development into fabrication and demonstrated yielding dies. Economically, however, the result depended on everything that came afterward: process qualification, yield learning, product selection, production volume, and the rollout of later RG generations. The announcement was consequently a sign of where Micron’s NAND manufacturing was heading, not proof that the entire market had already received cheaper or faster 128-layer storage.
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