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Reuters reported on September 4, 2024, that Broadcom’s early evaluation of Intel’s 18A manufacturing process had disappointed the chip designer and had not advanced to a high-volume-production commitment. That was a meaningful setback for Intel Foundry, but it was not public proof that 18A had failed across the board. Broadcom had not announced a definitive rejection, while Intel said its process was “powered on, healthy and yielding well” and remained on track for high-volume manufacturing in 2025.
The short version
The reported problem concerned Broadcom’s customer-level testing, not a publicly documented industry-wide failure of Intel 18A. Reuters cited sources familiar with the matter, but the report did not disclose Broadcom’s exact test vehicle, measured yield, performance results, or the specific reason the evaluation fell short.
Broadcom was reportedly still evaluating Intel Foundry’s products and services at the time. That makes “Broadcom canceled its Intel deal” or “18A was unusable” too definitive. The more accurate conclusion is that Intel had not yet demonstrated to Broadcom that its leading-edge foundry platform was ready for that customer’s production requirements.
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Intel disputed the negative implication without directly publishing Broadcom’s test results. In its September 4, 2024 statement, Intel said 18A was healthy, yielding well, had reached a defect-density level below D0 0.40, and remained on schedule for high-volume manufacturing in 2025.
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What Broadcom reportedly tested—and what is unknown
Reports indicated that Broadcom sent wafers or a test design through Intel’s 18A process. The public account does not establish whether this was:
- a small process test chip;
- a Broadcom production-oriented design;
- a specific IP block or test vehicle; or
- a broader qualification of Intel’s manufacturing, design enablement, packaging, and support ecosystem.
It also does not disclose whether the disappointing result involved wafer yield, functional yield, transistor performance, power, timing, design-rule compatibility, intellectual-property availability, cost, or schedule. “Underwhelming” describes the outcome; it does not identify the root cause.
That distinction matters because a customer evaluation can fail to meet expectations even when the underlying process is operating. An outside chip designer must use Intel’s process design kit, libraries, models, IP, manufacturing controls, and support workflows. A problem in any of those areas can prevent a design from reaching qualification without demonstrating that every 18A design has the same problem.
Why Broadcom’s evaluation mattered
Intel’s manufacturing recovery plan depended on moving through five process nodes in four years, a strategy commonly called “5N4Y.” Intel positioned 18A as the culminating leading-edge node and planned high-volume production for 2025. Its August 2024 process update described the first two Intel products using 18A as having powered on, booted operating systems, and yielded and performed well.
Those internal milestones were important, but a foundry cannot be judged solely by its own products. Intel Foundry also needed to show that outside companies could reliably move complex designs onto the process and manufacture them at predictable cost, performance, yield, and schedule.
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Broadcom was a significant evaluation opportunity because it develops sophisticated networking, connectivity, infrastructure, and custom silicon products. Its reported hesitation therefore affected Intel’s credibility with other potential customers, even though one customer does not represent the entire foundry market.
Process readiness is not the same as customer readiness
The central issue is the difference between two questions:
- Can Intel manufacture working silicon on 18A? Intel said yes, citing internal products that had powered on and a process it described as healthy and yielding well.
- Can an outside customer use 18A for a demanding production design? The Broadcom report raised doubts about whether Intel had met that narrower but commercially crucial standard at that point.
An internally designed chip gives Intel control over architecture, physical implementation, libraries, design schedule, debugging, and manufacturing decisions. An external customer brings its own design history, IP, electrical targets, package requirements, and production timetable. The customer also needs a stable platform rather than merely a functioning wafer.
That platform typically includes a mature process design kit, stable design rules, accurate extraction and timing models, reliable standard-cell and memory libraries, certified third-party IP, electronic-design-automation compatibility, packaging support, and a repeatable path from test wafers to volume production. The dossier does not establish that any one of these caused Broadcom’s reported disappointment; they are the categories that must be considered before blaming the transistor process itself.
What Intel’s D0 figure does—and does not—show
Intel’s reported D0 < 0.40 refers to defect density. It is not the final yield percentage of Broadcom’s particular chip.
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- Defect density estimates random defects per unit area.
- Die yield also depends on die size, layout, systematic defects, process variation, redundancy, and repair.
- Parametric yield measures whether working dies meet targets for voltage, frequency, power, timing, and related characteristics.
- Wafer and package yield can introduce additional losses after individual devices function.
A small test chip can show an acceptable result while a much larger or more complex customer design produces fewer usable dies or misses its electrical targets. Without Broadcom’s die area, test conditions, specifications, and measured results, Intel’s D0 statement cannot be converted into an exact Broadcom yield or treated as proof of commercial success.
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Intel describes 18A as combining two major process technologies: RibbonFET, a gate-all-around transistor architecture, and PowerVia, which moves power-delivery infrastructure to the back side of the wafer. Intel also links the node to advanced packaging capabilities such as newer EMIB and Foveros Direct technologies. Its published 18A overview claims up to 18% higher performance at the same power, 38% lower power at the same performance, and 30% greater chip density compared with Intel 3.
Those are Intel’s stated claims under specified conditions, not independent measurements of Broadcom’s design. PowerVia may improve power delivery and density, but adopting backside power can also add design complexity. A node can have strong technical potential while remaining difficult or expensive for a customer to migrate onto.
Possible explanations for the reported result
The public record does not identify a single cause. Plausible categories include:
- Intrinsic process performance: transistor speed, voltage scaling, power efficiency, or device variability may not have met the customer’s targets.
- Manufacturing yield: random or systematic defects, wafer-to-wafer variation, or edge-to-center differences may have affected usable output.
- Design enablement: the PDK, design rules, extraction flows, timing models, or EDA integrations may not have been mature enough for the design.
- IP and libraries: standard cells, SRAM, I/O, SerDes, memory, or third-party interface IP may have required further qualification.
- Design migration: porting a design from another foundry can require substantial changes, particularly for analog, mixed-signal, memory, and power-delivery blocks.
- Commercial execution: wafer pricing, capacity, risk-sharing, packaging, testing, or delivery dates may have made the program unattractive even if the silicon was technically functional.
Nothing in the reported account allows these possibilities to be ranked confidently. In particular, the report does not prove that Broadcom’s outcome was caused by a basic defect in the 18A transistor architecture.
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How to reconcile the two accounts
Intel’s statement that its own 18A products had powered on and were yielding well does not necessarily contradict a customer-specific setback. The statements concern different designs, conditions, and readiness criteria.
Likewise, Broadcom’s reported disappointment does not prove that Intel’s internal data was false. Intel may have had working internal silicon while still facing unresolved issues in customer design flows, IP, performance targets, or production economics.
The most precise reading is that Intel had evidence of internal process functionality, while Broadcom’s evaluation questioned whether that functionality had translated into a sufficiently predictable external foundry platform.
Independent reader supportYour contribution helps us test, update, and keep practical guides available for everyone.What remained unanswered on September 4, 2024
The report left several material questions open:
- What exact wafer, test chip, or production-oriented design did Broadcom evaluate?
- Was the evaluation an early technical experiment or a formal production-qualification gate?
- What were the measured functional, parametric, wafer, and package yields?
- Did the design miss frequency, power, timing, area, or reliability targets?
- Were the problems repeatable across wafers and lots?
- Did Broadcom continue evaluating Intel Foundry?
- Was there an existing production commitment to delay or cancel?
- Did other customers encounter similar issues?
Until those questions are answered with attributable evidence, “18A failed” is a broader claim than the available reporting supports.
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What later production evidence means
Intel later described 18A as having entered production in 2025 in an update covering process milestones and future technology. That is evidence that the node progressed beyond its earlier development stage, but it does not retroactively prove that Broadcom’s 2024 evaluation succeeded or that no customer-specific problems existed.
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Production status and customer qualification are related but distinct milestones. A process may enter production for Intel products while external customers continue to assess design enablement, capacity, yield, cost, and schedule. Conversely, a later customer commitment would be stronger evidence of foundry maturity than a general statement that the process entered production.
What would demonstrate a real recovery?
The most persuasive follow-up evidence would include:
- named external customers and publicly disclosed tape-outs;
- production commitments or recurring foundry revenue;
- measured yield disclosures tied to identifiable test chips or products;
- rising wafer volumes and stable delivery schedules;
- mature PDK, library, and third-party-IP milestones;
- independent test-chip results; and
- customer statements confirming successful qualification.
Investors and industry observers should also distinguish a one-off demonstration from repeatable manufacturing. The strategic test for Intel Foundry is not simply whether one 18A chip can boot. It is whether multiple external customers can use the platform predictably enough to risk expensive, high-volume products.
Bottom line
Reuters’ report was a meaningful credibility setback for Intel Foundry: Broadcom’s early 18A evaluation reportedly disappointed, and the customer was not ready to make the hoped-for high-volume commitment. But the public evidence does not establish poor overall 18A yield, a permanent Broadcom exit, or an intrinsic failure of Intel’s process technology.
Intel’s internal silicon and D0 claims addressed process progress from the company’s perspective. Broadcom’s reported experience addressed the harder commercial question of whether an outside customer could achieve its own production requirements. Intel ultimately needed to prove the latter through repeatable external qualification, not just working internal products.
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