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Intel 14nm was a manufacturing generation, not a transistor with a gate that measured exactly 14 nanometers. Introduced with Broadwell, it paired second-generation Tri-Gate FinFETs with tighter pitches, redesigned fins, new interconnect features and increasingly refined process variants. Its significance lies in how those pieces worked together—and how Intel extended the process family across several generations of processors.
What Intel meant by “14nm”
A process node is the name of a manufacturing generation, not a single measurement shared by every feature on a chip. Intel’s 14nm process had a 42nm fin pitch, a 70nm transistor gate pitch and a 52nm interconnect pitch. None of those dimensions is 14nm. The label is best read as the generation name for an integrated platform: transistor design, materials, lithography, wiring, design rules and manufacturing methods.
That distinction also matters when comparing companies. “14nm” at Intel and “14nm” at a foundry do not guarantee matching transistor dimensions or density. Intel’s later explanation of process naming discusses why node labels ceased to correspond directly to gate length: Intel’s explanation of process-node names.
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Where 14nm sat in Intel’s process history
Intel introduced its Tri-Gate transistor at 22nm. The move to 14nm therefore refined an existing three-dimensional transistor approach rather than introducing FinFETs to Intel for the first time. Intel’s Tri-Gate transistor announcement
| Intel generation | Transistor approach | Representative role |
|---|---|---|
| 32nm | Planar CMOS with high-k metal gate | Pre-FinFET generation |
| 22nm | First-generation Tri-Gate FinFET | Ivy Bridge |
| 14nm | Second-generation Tri-Gate FinFET | Broadwell |
| 10nm | More aggressive FinFET scaling | Successor that arrived later than planned |
| Intel 7 and later names | Later process generations and refinements | Subsequent Intel products |
Broadwell was the first Intel product manufactured on 14nm. Skylake followed on 14nm; Kaby Lake and Coffee Lake used optimized versions of the process. Intel also used 14nm for the Skylake-SP generation of Xeon Scalable servers. These were different product designs, not identical chips simply relabeled with new generation names.
| Product family | Role in the 14nm story | Intel source |
|---|---|---|
| Broadwell | First major client generation on Intel 14nm | Broadwell product information |
| Skylake | Major architectural generation manufactured on 14nm | Skylake product information |
| Kaby Lake | Generation described by Intel as using optimized 14nm | Kaby Lake product information |
| Coffee Lake | Further-optimized 14nm generation | Coffee Lake product information |
| Xeon Scalable, Skylake-SP | Server generation based on 14nm | Xeon Scalable technical overview |
How a Tri-Gate FinFET works
A planar MOSFET has a channel lying horizontally beneath its gate. A FinFET raises the channel into a narrow silicon ridge, or fin. In Intel’s Tri-Gate design, one gate electrode wraps over the fin’s top and down both sidewalls. “Tri-Gate” describes the three surfaces controlled by that gate; it does not mean three independent gates.
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Because the gate controls more of the channel’s surface, it can exert stronger electrostatic control than a planar gate. That helps the transistor carry current when on while limiting leakage when off, supporting smaller devices and useful performance. The basic structure and rationale are described in Intel’s Tri-Gate explanation.
FinFET width is also quantized: designers typically adjust drive strength by choosing one or more fins rather than continuously widening a flat channel. If a fin supplies more effective channel width, a circuit may meet its target with fewer fins, reducing device area and potentially capacitance and routing demand.
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What changed between Intel 22nm and 14nm
Intel’s published comparison shows that different dimensions scaled by different amounts. Its 14nm pitch figures were substantially smaller than the cited 22nm values, while the SRAM cell area also fell. These are Intel-reported process figures, not universal measures for every circuit layout. Intel’s 14nm technical presentation
| Metric | Intel 22nm | Intel 14nm | 14nm value relative to 22nm |
|---|---|---|---|
| Fin pitch | 60nm | 42nm | 0.70× |
| Transistor gate pitch | 90nm | 70nm | About 0.78× |
| Interconnect pitch | 80nm | 52nm | 0.65× |
| SRAM cell area | 0.108µm² | 0.0588µm² | About 0.54× |
Pitch is spacing, not the node name
Pitch describes the repeat spacing of structures. Fin pitch is the spacing between neighboring fins; gate pitch is the repeating spacing of transistor gates; interconnect pitch describes spacing in the wiring stack. These measures affect how much circuitry can fit, but they do not alone determine the density or speed of a complete design.
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Intel presented its 14nm fins as taller and thinner than its 22nm fins. A taller fin gives the gate more sidewall channel to control, increasing effective channel width in a compact footprint; a thinner fin can improve control over the channel. The trade-off is more demanding fabrication: fin shape, dimensions and placement must be controlled closely, and process variation can affect transistor behavior.
Fewer fins for a given drive target
When each fin contributes more effective channel width, a design may need fewer fins to reach a target drive strength. Fewer fins can save area and reduce capacitance, but the result depends on the cell and circuit. Designers still choose among speed, leakage, area and power targets.
Lithography and the wiring stack
Intel’s 14nm process used self-aligned double patterning to form features at pitches that were difficult to achieve with one conventional optical exposure. Multiple patterning enables tighter layouts, but requires more process steps and careful control of pattern placement, adding manufacturing complexity and potentially affecting cost, cycle time and yield. EE Times reported Intel’s use of self-aligned double patterning and Intel’s cost-per-transistor claim: EE Times’ coverage of Intel 14nm.
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Intel’s 14nm material also identifies air gaps in the interconnect context. Air has a lower dielectric constant than typical insulating materials, so replacing some dielectric around wires with air can reduce parasitic capacitance. Lower capacitance can help signal delay and switching energy, especially where wiring is a significant part of a circuit’s load. It is not a blanket speed boost: the effect depends on which wires use the gaps, their lengths and whether the circuit is limited by wiring, transistor drive, memory or thermal constraints.
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Intel 14nm was not an EUV process. EUV is a lithography exposure technology; FinFET describes a transistor architecture; 14nm is a process-generation label. They refer to distinct aspects of semiconductor manufacturing.
What 14nm could mean for performance, power, density and cost
Performance
Tighter geometry and transistor engineering can support higher drive current or faster switching, but a process does not set a processor’s performance by itself. Microarchitecture, cache, core count, voltage, frequency targets, turbo behavior, thermal limits, package and power delivery all influence the final product.
Power
Better gate control can reduce leakage, while lower capacitance can reduce energy per transition. Yet a smaller or more efficient process does not guarantee a lower-power chip: a design may spend its transistor and power budget on more cores, larger cache, graphics or higher clocks.
Density
Density comes from several elements working together: pitch scaling, fin geometry, standard-cell design, SRAM scaling and layout rules. A specific metric—such as SRAM cell area or a stated logic-density methodology—is more informative than comparing node names alone.
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- Compatible with Intel 600-series (with potential BIOS update) or 700-series chipset-based motherboards
- DDR4 and DDR5 platform support cuts your load times and gives you the space to run the most demanding games
Cost
Intel argued that aggressive area scaling lowered cost per transistor. Smaller dies can yield more potential chips from a wafer, but the wafer itself may require more complex processing. The useful economic measure is the cost of a functioning die or usable transistor, not wafer cost in isolation. Intel’s published claims should be read as Intel’s comparisons, not as an independently universal result.
Intel’s published density examples—and their limits
In its 14nm technical presentation, Intel reported a Broadwell example with about 1.3 billion transistors against about 960 million in a Haswell comparison, describing the Broadwell die as 37% smaller and containing 35% more transistors. Intel also cited up to 2.2× transistor-density improvement in that comparison. These are Intel’s figures for the configurations and comparison basis it selected, not a promise that every 14nm circuit is 2.2 times denser than every 22nm circuit.
Whole-die comparisons can reflect more than process scaling: product configuration, cache and graphics blocks, die-area definitions and the chosen density methodology matter. The same Intel presentation reports the SRAM cell areas shown above; SRAM is a useful, specific reference, but it is not a complete measure of logic density.
Independent reader supportYour contribution helps us test, update, and keep practical guides available for everyone.Why Intel 14nm lasted across so many products
Broadwell began the 14nm product era, and Intel subsequently used refined 14nm processes in multiple client and server generations. Kaby Lake and Coffee Lake were described by Intel as optimized 14nm implementations. Intel’s 10nm successor was delayed, extending 14nm’s commercial life, while continued process learning and product-specific tuning let Intel target different combinations of frequency, leakage, yield, core count and power.
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What 14nm+, 14nm++ and later labels mean
Intel publicly described later products as using optimized 14nm technology, but there is no single public specification that assigns every plus-marked derivative a fixed fin height, pitch change, density gain or voltage reduction. Names such as 14nm+, 14nm++ and 14nm+++ are common in technical coverage and enthusiast discussion; they should be understood as shorthand for refinements, not as a standardized measurement scale.
Those refinements could support different goals—higher frequency, improved low-voltage behavior, leakage control, yield or product flexibility—but the exact changes and results varied by implementation. Intel’s product descriptions for Kaby Lake and Coffee Lake use the term optimized rather than specifying one universal physical change for each iteration.
How to compare Intel 14nm with another company’s node
Do not infer equivalence from labels such as Intel 14nm, Samsung 14nm or TSMC 16nm. A meaningful comparison needs matched metrics and conditions. Useful questions include:
- What are the contacted gate pitch, fin pitch and minimum metal pitch?
- What SRAM cell area is reported, and under what cell design rules?
- How does the source define logic density?
- How does transistor performance compare at a matched voltage?
- What power is required at a matched performance target?
- How do complete products compare when architecture, core count, packaging and thermal limits are considered?
Even these measures describe different parts of the story. A denser SRAM cell does not establish CPU performance, and a fast transistor does not guarantee a faster processor.
Intel 14nm in the 2026 context
As of August 2026, Intel 14nm is a historical generation, not the company’s leading-edge process. Intel’s public foundry portfolio uses newer names including Intel 3, Intel 18A and Intel 14A, and Intel and UMC are developing a 12nm FinFET platform. That does not make every mature process useless: older nodes can remain suitable for products whose economics, longevity or design requirements do not call for the newest technology. Intel’s process portfolio
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