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A planar vertical NPN transistor is built by patterning and doping silicon in stages: a collector region is formed, a P-type base is created inside it, and an N+ emitter is formed inside the base. In a more useful integrated structure, an N+ buried layer and a deep N+ sinker provide a lower-resistance route to the collector, while deep P-type regions isolate the device from its neighbors.
The steps below explain a representative educational bipolar or BiCMOS flow—not a current Analog Devices production recipe or a specification for any particular foundry process. The chapter “Semiconductor Processing of NPN Transistors” appears in the Designing Analog Chips textbook on All About Circuits.
What semiconductor processing means
Semiconductor processing is the sequence of operations that turns a silicon wafer into working devices and interconnections. Depending on the process, these operations include growing or depositing films, patterning them with lithography, etching, adding dopants, annealing, opening contacts, depositing and patterning metal, and applying passivation.
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Three related terms are useful to keep separate:
- Device structure is the final arrangement of regions and contacts—for example, an N+ emitter inside a P base inside an N-type collector.
- Process flow is the ordered set of manufacturing steps used to create that structure.
- Process technology encompasses the materials, masks, thermal steps, design rules, available device options, and electrical targets used to manufacture and design with it.
A planar process builds and connects device regions at or near a relatively flat wafer surface. Silicon dioxide and other insulating films protect the surface and can act as masks that block dopants or define where an etch, implant, or contact opening occurs. Thin-film interference can make oxide thickness appear as different colors, which historically also helped operators judge film thickness visually.
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The repeating patterning cycle
Photolithography transfers a pattern from a mask to a layer on the wafer. A simplified cycle is:
- Grow or deposit an insulating film, commonly an oxide or an oxide-and-nitride stack.
- Coat the wafer with photoresist.
- Align a mask and expose the resist to light.
- Develop the resist to remove either exposed or unexposed areas, depending on the resist type.
- Etch the exposed portions of the underlying film.
- Strip the remaining resist.
- Carry out the step defined by the opening, such as diffusion, implantation, or contact formation.
- Clean and prepare the wafer for the next layer or mask; oxide may be regrown or another film deposited.
With positive resist, exposed regions are generally removed during development. With negative resist, exposed regions generally remain. Wet chemical etching can proceed sideways beneath the resist, so the etched opening may be wider than the mask opening. Plasma etching can produce more directional profiles, though the result depends on the material and recipe. In either case, the final junction or feature does not necessarily line up exactly with the drawn mask edge.
How dopants enter silicon
NPN fabrication relies on carefully placing impurities, or dopants, in silicon. A dopant changes the balance of mobile charge carriers. In silicon, boron is a conventional P-type dopant; arsenic and antimony are N-type dopants. Polarity matters: boron is not an N-type dopant.
Thermal diffusion
In thermal diffusion, dopant atoms from a gas or solid source enter silicon at elevated temperature. Concentration usually falls with depth, and the dopant spreads both vertically and laterally. Lateral spread means the finished junction can extend beneath the edge of a mask opening, changing effective device dimensions and spacing.
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Diffusion also consumes thermal budget. Later hot steps can move dopants that were introduced earlier, so a process must account for cumulative heat exposure rather than treating each step in isolation. The textbook’s example discusses furnace temperatures above approximately 1,000 °C; that is an illustrative process description, not a universal temperature for modern bipolar manufacturing.
Ion implantation
In ion implantation, ionized dopant atoms are accelerated into silicon. Implant dose and approximate depth can be controlled more directly than in a simple diffusion step, making implantation useful for shallow or shaped profiles. The implant disrupts the silicon crystal lattice, so a subsequent anneal is used to repair damage and electrically activate the dopants. Later thermal cycles can still redistribute them. Implant energy depends on the dopant species, desired depth, dose, and process; no single voltage describes every implant.
Start with the simple planar NPN
A conceptual vertical NPN can be built from a P-type silicon substrate by forming an N-type collector region, a P-type base within the collector, and an N+ emitter within the base. Contact openings are made and conductive material is added to contact the emitter, base, and collector. The transistor is called vertical because carriers travel mainly from the emitter down through the base into the collector, rather than chiefly sideways across the wafer surface.
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The simple structure exposes a key design problem: collector resistance. The collector must be doped lightly enough, and often made thick enough, to support the desired voltage without premature breakdown. But a lightly doped collector has higher resistance, particularly along the path toward the substrate. That series resistance can reduce voltage available to the circuit and affect speed and power dissipation.
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Epitaxy and the buried collector layer
Epitaxy grows a single-crystal silicon layer on the wafer, with controlled thickness and doping. A lightly doped N-type epitaxial layer can serve as the active collector region. Its thickness and doping help determine voltage capability, resistance, and junction properties. Epitaxy also allows a heavily doped layer to be placed beneath that active region.
That lower layer is the N+ buried layer. It is formed before the epitaxial layer grows over it. The buried layer offers a heavily doped, lower-resistance route for collector current and connects to a deep N+ region added later. It is not itself a surface contact: a sinker is needed to bring the buried layer’s electrical path up to the surface.
These features involve trade-offs. A more heavily doped collector path can reduce resistance, but high doping near a junction can reduce breakdown capability. A thicker or more lightly doped epitaxial collector can improve voltage handling but increase resistance and may affect capacitance and area. There is no single epitaxial thickness or buried-layer design that is best for every voltage, speed, and layout target.
Isolation and the collector sinker
Deep P-type isolation
In a junction-isolated structure, a deep P-type region reaches the P-type substrate and surrounds the N-type collector island. The P–N junction between the island and its surroundings isolates neighboring devices when it is reverse-biased. In the textbook’s conceptual example, the substrate is held at the circuit’s most negative potential to maintain that condition.
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Junction isolation is therefore a bias-dependent arrangement, not an unconditional barrier. Incorrect biasing can forward-bias an isolation junction; junction capacitance and substrate currents can also couple noise between devices. Isolation regions take up area, and mixed bipolar/CMOS designs must account for additional parasitic paths and latch-up-related risks.
N+ collector sinker
The sinker is a deep N+ region that connects the collector contact at the surface to the N+ buried layer. It gives current a lower-resistance path than traveling through the lightly doped epitaxial collector alone. The sinker improves the collector connection, but it consumes layout area and forms junctions with the surrounding P-type isolation and substrate, adding capacitance. A low-resistance semiconductor path also does not eliminate contact resistance: the semiconductor-to-metal interface and current crowding still matter.
A representative integrated NPN flow
The following sequence shows the roles of the main regions in a simplified bipolar or BiCMOS device. Actual processes can change the ordering, share masks, use different isolation structures, or add steps.
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- Pattern and form the N+ buried layer. This heavily doped region will lower collector spreading resistance beneath the future active collector.
- Drive in or anneal the buried-layer dopant. The thermal step establishes the intended buried profile, subject to the process’s overall thermal budget.
- Grow lightly doped N-type epitaxial silicon. This layer provides the active collector region above the buried layer.
- Form deep P-type isolation. The isolation regions reach the P-type substrate and define N-type collector islands.
- Form the N+ sinker. This deep region joins the surface collector contact to the buried layer.
- Form the P-type base. Its depth and lateral dimensions help set the transistor’s active base geometry.
- Form the N+ emitter inside the base. This creates the emitter-base junction.
- Open contact windows. Pattern and etch openings where the emitter, base, and collector are to be contacted.
- Deposit and pattern interconnect metal. Aluminum is one example used in textbook descriptions; current metal stacks vary by process.
- Apply protective passivation and open bond-pad areas. Passivation protects the finished surface, while pad openings allow external electrical connection.
Process options can differ substantially: a foundry may use implants instead of some diffusion steps, trench or dielectric isolation rather than junction isolation, silicide, multiple interconnect layers, chemical-mechanical polishing, or specialized high-voltage and RF device structures. This outline is a way to understand the device, not a foundry recipe or a statement about a particular Analog Devices process.
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How process choices affect electrical behavior
- Collector resistance and breakdown: A heavily doped or short collector path lowers series resistance, while a lightly doped or thicker collector generally supports higher voltage before breakdown. The design balances the two.
- Base width, gain, and speed: A narrow base can reduce carrier transit time and support higher-frequency operation. Making it too narrow can increase sensitivity to variation, leakage, punch-through, or breakdown constraints.
- Capacitance and layout: Junction area and spacing affect capacitance. The isolation wall and sinker lower resistance in useful ways but add area and parasitic junction capacitance.
- Diffusion and alignment: Lateral dopant spread changes effective region dimensions. Mask alignment and dopant profiles therefore influence spacing, capacitance, and device consistency.
- Isolation and substrate coupling: Junction isolation works only under appropriate bias conditions and can provide paths for substrate noise or injected current.
- Contacts and surface quality: Clean contact openings, interface preparation, contact materials, and anneals affect resistance and leakage. Oxide and passivation protect the surface, but contamination at openings can still degrade device behavior or yield.
These relationships explain why a cross-section alone does not specify a transistor’s performance. Electrical ratings such as gain, breakdown voltage, or cutoff frequency depend on detailed geometry, doping profiles, materials, processing, and operating conditions.
Why integrated circuits use NPN transistors—and where BiCMOS fits
NPN transistors have long been valuable in analog ICs because, in suitable designs, they can provide high transconductance for a given bias current, useful current gain, and strong speed or noise performance. Matching also benefits from appropriate layout and process control. These are design advantages, not a claim that NPN is always better than CMOS or PNP; the best device depends on voltage, current, noise, speed, area, matching, and cost requirements.
BiCMOS combines bipolar devices with CMOS transistors. Bipolar devices can serve demanding analog, high-speed, or current-driving functions, while CMOS can provide dense digital logic and often low static power. Integrating more device types can share process steps, but it also adds masks, thermal and materials constraints, layout rules, and potential compromises. Many analog processes therefore offer a selected set of device options rather than every possible transistor type.
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What this textbook flow does—and does not—tell you
The All About Circuits chapter is useful for understanding oxidation, lithography, etching, diffusion, epitaxy, implantation, buried layers, sinkers, and junction isolation. It does not establish a current Analog Devices process node, fab location, PDK version, transistor rating, or proprietary production sequence. “Modern NPN” is not one universal structure: voltage class, isolation method, epitaxial design, metal stack, and device options differ between manufacturing processes.
For circuit design, use the foundry’s process documentation and design kit for the actual device and revision. The educational sequence explains why the regions exist; only process-specific data can define their permitted layout and electrical limits.
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