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Arm Total Design is a commercial partner ecosystem for building custom Arm-based data-center chips—not a finished processor or a self-service chip-design kit. It combines Arm Neoverse Compute Subsystems (CSS), which provide a pre-integrated compute foundation, with partners in chip design, IP, EDA, manufacturing, packaging, firmware, and software. The aim is to reduce duplicated integration work and make custom silicon more practical, while leaving customers responsible for the product’s architecture, validation, costs, and deployment.
What Arm Total Design is—and is not
Arm Total Design connects customers developing custom systems-on-chip (SoCs) and chiplets with Arm technology and participating companies across the semiconductor supply chain. Arm describes the program as providing access to Neoverse CSS, pre-integrated IP and EDA tools, design services, foundry support, and commercial software and firmware support. Arm’s program page outlines the offering.
It helps to distinguish four terms:
- Neoverse CPU IP: individual Arm processor cores and related licensed technology.
- Neoverse CSS: a more integrated, pre-validated compute subsystem built around Neoverse cores and system components.
- Arm Total Design: the wider partner ecosystem intended to help customers build and deploy a customized product around CSS.
- The finished SoC: the customer’s chip, which may combine the compute subsystem with proprietary accelerators, memory and I/O, security, networking, chiplets, packaging, firmware, and software.
Thus, Total Design is neither a retail development board nor a guarantee that a customer can freely modify every part of a CSS. Public materials do not set out every licensing boundary, supported configuration, or commercial term; those details need to be confirmed with Arm and the relevant partners.
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Why build a custom data-center chip?
Cloud and infrastructure operators run workloads at scale and can sometimes justify silicon tailored to their own needs. Those workloads may include web services, databases, storage, networking, analytics, media, security, AI inference, or support for AI training. A purpose-built design can let an operator choose how CPU resources, memory bandwidth, I/O, and accelerators fit together rather than accepting a merchant processor’s fixed configuration.
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The potential payoff is not just a faster CPU benchmark. Power affects how many servers fit within a rack or facility, cooling requirements, electricity costs, and the capacity an operator can deploy. Customers may also value roadmap control, supply planning, or tighter integration with a proprietary accelerator. Arm positions Neoverse and CSS around performance-per-watt and total-cost-of-ownership goals, but outcomes depend on the finished chip, software, server design, workload, and facility. Arm’s positioning is not independent proof of a system-level saving.
Custom silicon is most compelling when a workload is predictable, deployment volume is large enough to spread development costs, or strategic control over the hardware is especially valuable. It is much harder to justify for uncertain workloads or low-volume products.
What Neoverse CSS contributes
A CSS gives a customer a more complete starting point than licensing processor cores alone. Arm describes CSS as a pre-validated subsystem incorporating Neoverse cores, coherent mesh interconnect, memory controllers, and other system IP. This can spare a project from building and validating every CPU-side foundation block independently, though it does not remove product-specific integration and verification.
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Arm’s CSS V3 specifications describe support for up to 64 Neoverse V3 cores per subsystem, up to 12 DDR5/LPDDR5 memory channels, and up to 64 lanes of PCIe Gen5 or CXL I/O. Arm also lists UCIe 1.1 and custom die-to-die PHY support for chiplet connectivity. These are vendor-published specifications, not independent benchmarks, and actual configurations depend on the licensed design.
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Arm has also made comparative performance claims for particular products: it said CSS N3 offered 20% higher performance per watt than CSS N2, and CSS V3 offered a 50% performance-per-socket improvement over CSS N2. These figures refer to Arm’s stated comparisons, not a universal result for every application or finished system. See Arm’s announcement on AI infrastructure for context.
CSS is a compute foundation, not the whole product. A customer may add an AI accelerator, encryption or compression engines, custom memory or networking functions, telemetry, security features, and other proprietary blocks. The resulting design can be differentiated without requiring the customer to invent a new CPU microarchitecture.
How a Total Design project can work
- Set the workload and system target. Define throughput and latency goals, CPU count, memory capacity and bandwidth, accelerator needs, connectivity, security, power envelope, rack constraints, software requirements, and expected volume.
- Choose a suitable CSS. Compare the required performance, power, core count, memory and I/O, scalability, process options, and potential chiplet approach. Arm positions V-series products such as CSS V3 for cloud CPUs and AI-infrastructure-related designs, while N-series products are associated with energy-efficient infrastructure workloads. The exact available configurations and commercial terms are not fully specified in public product pages.
- Plan the custom elements. Decide which accelerators, interfaces, security functions, memory features, or customer-specific blocks belong in the chip, and which should be separate dies or components.
- Assemble the implementation team. The customer can draw on ecosystem partners for architecture, RTL integration, EDA, physical design, verification, test, high-speed connectivity, package design, foundry enablement, firmware, and software. Arm’s overview of Total Design for AI describes this partner model.
- Verify, manufacture, and deploy. The project still must complete design verification and signoff, tape out, fabricate wafers, package and test parts, bring up silicon, enable firmware and operating systems, qualify systems, and ramp production. A reusable subsystem can reduce some work, but advanced-node development and manufacturing remain lengthy and financially risky.
Chiplets: useful, but not easy by default
Chiplets can let a product combine distinct dies—for example, general-purpose Arm CPU compute, an AI accelerator, high-bandwidth memory interfaces, networking, security, and customer-specific logic. CSS V3’s listed UCIe and custom PHY support, and the Arm Chiplet System Architecture, provide building blocks for such designs. The Open Compute Project also describes CSS chiplet use and AMBA CHI C2C in its CSS chiplet material.
But chiplet support does not make integration automatic. Teams still need to resolve die-to-die protocols, latency, coherency, power delivery, thermal hotspots, signal integrity, package yield, test coverage, security boundaries, and how software sees heterogeneous resources. Whether chiplets improve cost, performance, or schedule depends on the particular design and manufacturing plan.
Examples announced by Arm
Microsoft Azure Cobalt
Arm has identified Microsoft’s Azure Cobalt processor as a custom cloud CPU based on Neoverse CSS. It illustrates why a hyperscaler might use a reusable compute foundation while tailoring a processor for its own infrastructure. It does not establish that all CSS-based chips have the same customization, performance, or deployment characteristics. Arm’s announcement about Microsoft’s custom silicon provides the source for the relationship.
Samsung Foundry, ADTechnology, and Rebellions
In October 2024, Arm announced a collaboration involving Samsung Foundry, ADTechnology, and Rebellions on an AI CPU chiplet platform. The announced design combined a Rebellions AI accelerator with an ADTechnology compute chiplet based on Neoverse CSS V3 and targeted cloud, HPC, and AI training and inference. The announcement associated the platform with Samsung’s 2-nanometer GAA process. Arm also cited an estimated 2–3× efficiency advantage for a specific GenAI workload. That is an announced estimate for a stated workload, not an independently verified general result or a guarantee for other systems. Details are in Arm’s announcement.
Socionext and Alphawave
Arm has also highlighted a Socionext multi-core CPU chiplet based on Neoverse CSS for server CPUs, data-center AI edge servers, and 5G/6G infrastructure. Alphawave has been associated with connectivity IP and chiplet platforms used alongside CSS. These examples show the range of announced partner roles; they do not mean that every customer receives a turnkey design or that every partner is responsible for the complete SoC. Arm’s ecosystem announcement and AI-focused overview describe these initiatives.
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1Clear out junk files and repair common Windows errors2Scan for outdated or missing drivers - takes under a minute3Repair Windows errors before they cause bigger problemsMembership changes over time. Arm reported more than 20 ecosystem members within four months of launch and later described the ecosystem as approaching 30 participating companies in October 2024. Those are dated counts, not a current fixed total; the October 2024 announcement gives the later figure.
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Potential advantages:
- Less duplicated integration: a pre-integrated compute subsystem can reduce the need to assemble CPU-side infrastructure from individual blocks.
- Access to specialist capabilities: partners can supply design services, EDA, connectivity, packaging, foundry access, firmware, or software support the customer does not have in-house.
- More product control: customers can differentiate around the compute foundation with their own accelerator, memory, I/O, or security choices.
- A route to chiplet designs: CSS and partner technologies can support heterogeneous products, subject to the engineering and package constraints.
Arm markets CSS and Total Design as a way to accelerate development and reach production sooner. The mechanism is reuse of IP and access to partners, not a promised fixed schedule reduction. A project can still slip because of verification problems, partner coordination, process readiness, package challenges, software work, or production yield.
Costs and constraints remain substantial. A custom SoC may require significant spending on engineering, IP and EDA licenses, verification, masks, wafers, packaging, testing, software, board redesign, qualification, inventory, and long-term support. Pricing is not publicly listed as a simple package; licensing, royalties, engineering, support, and volume terms are negotiated. The investment case generally improves with scale or a particularly valuable workload advantage.
Responsibility is distributed. An ecosystem is not necessarily one contract, one vendor, or one accountable party. Customers need to know who owns overall integration, verification, post-silicon debug, software, foundry qualification, and escalation when components from multiple suppliers interact.
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Who should evaluate Arm Total Design?
It is most relevant to hyperscalers, large infrastructure providers, accelerator companies, networking vendors, and other organizations with stable workloads, a credible high-volume business case, and the ability to fund a multiyear silicon program. It can also suit a company whose strategic differentiation lies in integrating CPU compute with proprietary accelerators or system IP, while relying on outside partners for parts of implementation.
It is less likely to fit a small company with low or uncertain volume, a short-lived product, no budget for validation and software enablement, or no fallback if tapeout slips. Such customers may be better served by a merchant processor, accelerator platform, cloud instance, or turnkey design engagement.
Questions to ask before committing
- Economics: Is the workload stable and the projected volume sufficient to amortize development and qualification? Does the expected benefit hold at rack or fleet level?
- Technical fit: Does the chosen CSS support the needed memory, I/O, coherency, process, and package approach? Which blocks are fixed, configurable, or separately licensed?
- Accountability: Which partner owns integration and verification? Who is responsible for bring-up, debug, and long-term support?
- Software and deployment: Can existing applications run as-is, or will they require recompilation or optimization? Will boards, power delivery, cooling, firmware, and server designs change?
- Risk management: What is the fallback if the schedule slips? Are all required IP blocks compatible and qualified for the selected process and package?
Alternatives to consider
- License Arm CPU IP independently: offers more architectural freedom than starting with CSS, but leaves more subsystem integration and validation responsibility with the customer.
- Buy a merchant Arm server CPU: avoids most silicon-development risk and accelerates procurement, at the cost of less control over the processor and platform.
- Use an x86 server platform: can be the more straightforward option where broad compatibility, mature software, and established procurement channels dominate. Customization is more limited, and performance or efficiency comparisons depend on the workload and product.
- Deploy GPUs or other accelerators: can provide a faster route to AI capability without designing a new CPU SoC, but may bring platform dependence and less workload-specific integration.
- Hire an ASIC design house: can simplify project delivery through a more turnkey services relationship, though it may add service costs and dependence on the provider’s preferred IP and manufacturing relationships.
Arm supplies architecture and IP; foundries manufacture the chips, with design and implementation work distributed across customers and partners. Total Design coordinates access to this ecosystem—it does not make Arm the sole manufacturer or operator of every resulting product.
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