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Add power-factor correction (PFC) when harmonic-current compliance, universal-input operation, input-current reduction, DC-bus regulation, hold-up time, or power density justify the extra stage. Do not add it merely because modern AC–DC supplies are expected to have PFC. The correct choice depends on the product’s market, applicable standards, power level, line range, load profile, efficiency target, thermal budget, EMI constraints, and development risk.
For most medium- and high-power universal-input supplies, the lowest-risk starting point is a conventional two-stage design: a bridge rectifier and active boost-PFC stage feeding a regulated high-voltage DC bus, followed by an isolated DC–DC converter.
What PFC changes in an offline power supply
A typical offline switch-mode supply is arranged as:
AC input → fuse / surge protection / EMI filter → bridge rectifier → PFC stage → high-voltage DC-link capacitor → isolated DC–DC converter → output regulation / point-of-load conversion
The PFC stage shapes the input current so that it approximately follows the rectified mains voltage:
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iin(t) ∝ |vline(t)|
It therefore reduces harmonic current and improves true power factor. It also commonly regulates the downstream DC bus, allowing the isolated converter to operate from a more predictable input. See ST’s overview of single-phase PFC architectures for the relationship between boost, interleaved, and bridgeless implementations: ST single-phase PFC applications.
PFC does not eliminate all distortion, guarantee regulatory compliance, or automatically improve total efficiency. It is a front-end system decision, not simply a controller-IC selection.
Why a bridge-and-capacitor input has poor power factor
The simplest AC–DC input is:
AC → bridge rectifier → large electrolytic capacitor → DC–DC converter
The capacitor charges only when the instantaneous rectified line voltage exceeds the capacitor voltage. As a result, current flows in narrow pulses around the peaks of the AC waveform rather than continuously throughout each half-cycle.
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Those pulses create:
- High peak diode, fuse, connector, wiring, and EMI-filter current.
- Higher RMS line current than the delivered real power alone requires.
- Significant harmonic current.
- Greater conducted-emissions and thermal stress.
This is primarily a distortion problem, not necessarily a simple phase-shift problem. The current pulses can be centered around the voltage peaks while still producing poor total power factor because the current waveform is highly nonsinusoidal.
PF, THD, and efficiency are different measurements
True or active power is the power actually transferred to the load. Apparent power is the product of RMS voltage and RMS current. Displacement power factor describes phase shift between sinusoidal voltage and current, while distortion power factor describes degradation caused by waveform distortion. Total power factor combines both effects.
For a mostly sinusoidal mains voltage, a useful first-order relationship is:
Iline,rms ≈ Pin / (Vline,rms × PF)
For fixed real power, poor PF means higher RMS current. Onsemi’s design material explains this relationship and shows why a PF of 0.5 can require approximately twice the RMS current of a supply operating near unity PF: Onsemi PFC design notes.
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Is PFC required for your product?
Do not use “PFC is mandatory above 75 W” as a universal legal rule. That number is a common industry heuristic for some product categories, not a complete statement of IEC scope.
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The current consolidated listing for IEC 61000-3-2:2018+AMD1:2020+AMD2:2024 covers equipment with rated input current up to and including 16 A per phase connected to public low-voltage distribution systems. Its limits and test conditions depend on equipment classification. Products above that range may be subject to other requirements, including IEC 61000-3-12 or installation-specific limits.
Before choosing a topology, establish:
- Destination countries and regions.
- Whether the product connects to a public low-voltage supply.
- Rated input current per phase.
- Applicable equipment class: IT, lighting, appliance, industrial, medical, telecom, or another category.
- Product-specific safety, EMC, flicker, and harmonic-current requirements.
- Whether the measured non-PFC design already passes the applicable limits at every required operating point.
Compliance cannot be inferred from a PF reading of 0.99. Harmonic-current measurements must be made under the applicable standard’s specified line, load, and classification conditions.
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When PFC is usually compelling
- Universal input, such as approximately 85–265 VAC.
- Substantial continuous input power.
- Servers, telecom equipment, industrial supplies, large displays, lighting, battery chargers, appliances, and similar products.
- Strict harmonic-current requirements.
- A need for a predictable high-voltage DC bus.
- High power density or long, controlled hold-up time.
When it may not be justified
Small adapters, low-duty-cycle products, fixed-input designs, and products outside applicable harmonic-current requirements may not justify a dedicated active PFC stage. Passive PFC or no PFC can be reasonable when the measured input waveform passes the required limits and the added losses, size, cost, and complexity offer no meaningful product benefit.
Passive versus active PFC
| Approach | Strengths | Limitations | Good fit |
|---|---|---|---|
| None | Lowest cost, size, and complexity | Peaked current and high harmonic distortion | Low-power or lightly regulated applications where compliance is demonstrated |
| Passive | Simple, quiet, robust, little or no high-frequency control | Large magnetics, voltage drop, limited PF improvement, poor wide-range performance | Fixed-input, lower-power products with modest size and compliance demands |
| Active | High PF, low THD, regulated bus, good universal-input behavior | Additional switch, inductor, diode, sensing, EMI, thermal, and control work | Most modern medium- and high-power universal-input supplies |
Passive PFC can still be a sensible cost-driven choice, but its performance is less consistent across line voltage and load. Active PFC is normally the first architecture to evaluate when the supply must support a wide input range or demanding harmonic limits.
Choosing an active-PFC topology
Conventional boost PFC
A boost PFC stage uses the rectified AC input, an inductor, a controlled switch, a boost diode or synchronous path, and a high-voltage bus capacitor. The bus is regulated above the maximum rectified line peak, but there is no universal “correct” bus voltage. The target depends on line range, downstream converter requirements, hold-up time, semiconductor ratings, efficiency, and safety constraints.
The conventional bridge-plus-boost arrangement is usually the lowest-risk option because its current paths, protection methods, reference designs, and layout practices are well established.
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In CrM, also called transition mode, the inductor current returns to zero at the end of every switching cycle.
- Advantages: zero-current turn-on opportunity, reduced reverse-recovery stress, good efficiency at modest power, and relatively simple control.
- Costs: variable frequency, higher peak current, more difficult EMI-filter design, potentially high light-load frequency, and possible acoustic or control interactions.
Transition mode is commonly attractive for lower-power designs where low cost and simplicity matter. ST positions its transition-mode portfolio for lower-power applications and its CCM portfolio for higher-power operation: ST PFC controllers.
Continuous-conduction mode
In CCM, the inductor current remains above zero during normal operation.
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- Advantages: lower peak and RMS current for a given power, lower component stress, and suitability for higher-power operation.
- Costs: harder switching transitions, reverse-recovery stress, more demanding current-loop compensation, possible slope-compensation requirements, and greater sensitivity to current-sense noise.
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Interleaved PFC
Interleaving two or more PFC phases with phase displacement reduces input and bus ripple and distributes current across multiple inductors and switches.
It can provide:
- Lower per-phase current.
- Reduced ripple-current stress in the DC-link capacitor.
- Better thermal distribution.
- Higher practical power capability.
The trade-off is additional switches, drivers, sensors, control logic, current sharing, startup behavior, fault paths, and PCB area. Interleaving is not automatically more efficient once those additional losses are included. It is most compelling when ripple, thermal distribution, or power density justify the complexity.
Bridgeless and totem-pole PFC
Bridgeless arrangements reduce or remove the bridge rectifier’s high-current conduction loss. Totem-pole PFC uses active switches in place of part or all of the diode bridge.
The potential benefits are high efficiency and power density. The engineering costs include:
- Complex commutation and zero-crossing behavior.
- High-side and low-side gate-drive requirements.
- Dead-time and shoot-through management.
- Common-mode EMI.
- Reverse-conduction behavior.
- More demanding protection and fault analysis.
- Greater layout sensitivity.
SiC MOSFETs, silicon MOSFETs, and GaN devices may all be appropriate depending on voltage, frequency, cost, and control requirements. Onsemi’s discussion of bridgeless totem-pole PFC highlights the control and protection challenges: Onsemi totem-pole PFC overview.
Do not select totem-pole PFC solely because it has the highest headline efficiency. The complete product must benefit after gate-drive loss, EMI filtering, magnetic loss, thermal constraints, and validation effort are included.
Single-stage or two-stage PFC?
Two-stage architecture
AC → PFC boost → regulated HV bus → isolated DC–DC
Two-stage designs independently control input-current shaping and output regulation. They provide a predictable DC bus, simpler hold-up calculations, easier stage-by-stage optimization, and broad compatibility with flyback, LLC, phase-shifted full-bridge, and other isolated converters.
The costs are an additional switching stage, more components, more board area, and extra light-load losses. For a new medium- or high-power supply, this is generally the safest architecture to develop unless the product has unusually strict cost or size constraints.
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Single-stage PFC
Single-stage designs combine PFC and output-conversion functions. They can reduce component count and potentially lower cost, but input-current shaping, output regulation, energy storage, transient response, and light-load behavior become tightly coupled.
Choose single-stage PFC only when its compromises are acceptable for the actual load profile. Fewer components do not necessarily mean lower design risk.
System sizing: the numbers that matter
Worst-case input current
For a first-order estimate:
Iline,rms ≈ Pout / (ηPSU × Vline,rms × PF)
Use the lowest rated line voltage, minimum expected efficiency, and minimum expected PF for thermal and connector estimates. Peak current must be calculated separately because it depends on the selected mode, inductor, line angle, switching frequency, control law, and ripple target.
Power and efficiency budget
Approximate the DC–DC input power as:
PPFC,in ≈ Pout / ηDC-DC
and total AC input power as:
Pin ≈ Pout / (ηPFC × ηDC-DC)
Budget losses for the bridge, inductor copper and core, switch, diode or synchronous path, current sensor, controller, gate driver, snubbers, EMI components, and capacitor ESR. Evaluate the complete PSU rather than optimizing PFC efficiency in isolation.
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Available hold-up energy is approximately:
E = ½C(Vstart2 − Vstop2)
Increasing capacitance, bus voltage, or allowable bus-voltage drop increases available energy, but also affects inrush, cost, size, ripple-current heating, safety spacing, fault energy, and capacitor lifetime. A regulated PFC bus does not automatically provide long hold-up time, and it is not perfectly ripple-free: the twice-line-frequency power pulsation still appears as bus ripple and capacitor current.
Inductor, switch, and diode
Do not use one universal inductor equation without specifying whether the design is CCM, CrM, or DCM and how the controller operates. At minimum, define:
- Minimum and maximum line voltage.
- Power and load range.
- Switching-frequency or variable-frequency range.
- Target ripple current.
- Bus voltage.
- Duty-cycle range.
- Core saturation margin.
- Copper temperature, skin effect, and proximity effect.
The ideal boost relationship is:
Vout = Vin / (1 − D)
But the rectified input changes continuously through every half-cycle, so duty cycle and current stress must be checked at the worst line angle, usually near the lowest rectified input voltage.
Switch and diode ratings must include maximum bus voltage, line surge, drain-voltage overshoot, reverse-recovery stress, switching loss, gate-drive excursions, short-circuit behavior, and temperature derating.
Control-loop, startup, and downstream interaction
Most active-PFC systems have an inner current loop and an outer bus-voltage loop. The voltage loop is intentionally slow relative to the twice-line-frequency ripple so it regulates average bus voltage without trying to cancel every line-power pulse and thereby distorting the current reference.
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Important interactions include:
- Input-voltage feed-forward and current-reference scaling.
- Current-loop compensation and sense-noise immunity.
- Voltage-loop bandwidth and twice-line-frequency ripple rejection.
- Downstream converter power pulsation.
- Load steps and sudden load removal.
- Light-load burst or skip modes.
- Bus overvoltage during downstream shutdown.
- Brownout detection and restart.
- Startup power for the controller and isolated converter.
There is no universal loop bandwidth or control structure. The selected controller’s datasheet, compensation method, reference design, and measured plant must govern the implementation.
EMI, safety, and layout
PFC may solve a low-frequency harmonic problem while creating a high-frequency EMI problem. The design still needs a properly damped input EMI filter and careful control of switching-current paths.
Pay particular attention to:
- Differential-mode current from the switching loop.
- Common-mode current from high-
dv/dtnodes. - Bridge-diode recovery.
- MOSFET turn-on and turn-off speed.
- Gate-loop inductance and driver return paths.
- Kelvin connections for current sensing.
- Snubber placement.
- PFC-inductor winding capacitance.
- X-capacitor discharge.
- Y-capacitor leakage current.
- Creepage, clearance, and insulated heatsinks.
- Fuse, surge-protection, and inrush-limiter coordination.
- Bulk-capacitor stored energy and discharge time.
Minimize the hot switching loop. In a conventional boost stage, it includes the PFC switch, boost diode or synchronous path, DC-link capacitor, and return path to the switch. The exact loop changes with topology, so start with the controller manufacturer’s reference layout and then adapt it with measured parasitics in mind.
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The PFC bus is hazardous even after the AC input is removed. Design discharge paths, service procedures, insulation systems, fault clearances, and abnormal-operation behavior explicitly.
Silicon, SiC, and GaN
| Device technology | Typical reason to consider it | Important qualification |
|---|---|---|
| Silicon MOSFET and diode | Moderate frequency, moderate power, low cost, conventional design | Reverse recovery and switching loss can become significant |
| SiC diode or MOSFET | Higher power, high bus voltage, reduced reverse-recovery loss, higher efficiency | Device cost, gate drive, layout, and EMI still determine system benefit |
| GaN | Very high frequency and compact magnetics | Fast-switching layout, gate-drive behavior, dead time, and commutation must be tightly controlled |
Wide-bandgap devices do not automatically improve the complete PSU. Their value depends on switching frequency, gate-drive loss, commutation-loop inductance, EMI-filter size, thermal design, and the losses of the remaining bridge and magnetic components.
Validate beyond the nominal waveform
1. Simulate the operating envelope
- Startup and shutdown.
- Brownout and input interruption.
- Low-line full-load operation.
- High-line full-load operation.
- High-line light-load operation.
- Minimum load and no-load behavior.
- Load steps and input-voltage steps.
- Component tolerances and temperature extremes.
- Control-loop stability.
- Switch-voltage overshoot and inductor saturation.
2. Bring up the hardware safely
Use isolation, current-limited instrumentation, suitable differential probes, and correctly rated current probes. Verify gate signals before applying full mains. Begin with a resistive or electronic load, confirm controller supply sequencing, check current-sense polarity and scaling, and verify bus startup and shutdown behavior.
3. Measure the real design
- PF and individual harmonic currents.
- Input RMS and peak current.
- Input-current THD.
- Complete PSU and PFC-stage efficiency.
- DC-bus ripple and hold-up time.
- Switch, diode, inductor, and capacitor temperatures.
- Bulk-capacitor ripple current.
- Startup overshoot and shutdown discharge time.
4. Test faults and abnormal conditions
- Downstream short circuit or converter shutdown.
- PFC switch open and short failures.
- Boost-diode failure modes.
- Current-sense disconnection.
- Feedback disconnection.
- Brownout and repeated restart.
- Input surge and overtemperature.
- Load removal at high line.
5. Perform pre-compliance testing
Check conducted emissions, radiated emissions, harmonic current, flicker or voltage-change behavior where applicable, leakage current, dielectric strength, abnormal operation, and thermal safety. A vendor reference design demonstrates an implementation under stated conditions; it is not automatically a certified product.
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| Product situation | Likely starting point | Main risk |
|---|---|---|
| Very low power, fixed input, modest compliance burden | No PFC or passive PFC | Harmonic limits may fail across line and load |
| Universal-input adapter with meaningful continuous power | Conventional active boost PFC | Added light-load loss, EMI, and inrush |
| Several hundred watts | CrM/TM or CCM, selected by current, frequency, cost, and thermal targets | Peak-current or switching-loss trade-offs |
| Higher power with lower peak current requirements | CCM, possibly interleaved | Reverse recovery, sensing, compensation, and current sharing |
| High power density and maximum efficiency | Bridgeless or totem-pole architecture | EMI, commutation, gate drive, protection, and validation |
| Strong hold-up requirement | Two-stage PFC with deliberate bus-capacitor sizing | Inrush, stored energy, size, ripple heating, and safety |
| Light-load operation dominates | Evaluate burst behavior, standby power, PF degradation, and audible noise | Poor light-load PF and downstream control interaction |
Vendor portfolios can help narrow the implementation. ST provides transition-mode and CCM controllers, TI maintains PFC-and-LLC controller resources, and Onsemi provides CrM, CCM, interleaved, bridgeless, and totem-pole design resources. These pages are useful starting points, not substitutes for a product-specific design and compliance review: TI PFC and LLC resources and Onsemi PFC resources.
Final decision framework
- Define compliance first. Identify markets, equipment class, input current, and applicable harmonic, EMC, safety, and flicker requirements.
- Calculate the no-PFC baseline. Measure or estimate RMS current, peak current, harmonics, bridge loss, thermal stress, and compliance margin.
- Decide whether a regulated bus is useful. Consider universal input, downstream converter range, hold-up, transient response, and power density.
- Select the least complex topology that meets the requirements. Conventional boost PFC is usually the lowest-risk active solution.
- Choose CrM, CCM, or interleaving from current and thermal requirements. Do not use a fixed wattage boundary as a substitute for analysis.
- Consider bridgeless or totem-pole designs only when their efficiency or density benefit pays for the additional engineering.
- Validate PF, THD, efficiency, EMI, safety, thermal behavior, startup, faults, and light-load operation together.
The best PFC design is not the one with the highest nominal PF or the most advanced switches. It is the simplest architecture that meets the actual regulatory limits, line range, load profile, efficiency, thermal, EMI, safety, and product-cost requirements with enough validation margin for production.
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