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Codasip’s “custom, safe and secure” message describes a commercial approach to building RISC-V processor IP—not a single new core or a new RISC-V standard. It combines configurable processor designs and design tools, safety-oriented development processes, and security features including CHERI-based memory protection. The message was presented at the RISC-V Summit Europe 2025; since then, Codasip has announced a strategic pivot toward cyber-resilient and CHERI products, alongside a planned divestiture of its low-end processor business. Those changes matter when evaluating any product’s availability or support.
What Codasip announced at RISC-V Summit Europe 2025
Codasip’s presentation in Paris was a keynote and product update, not a new instruction-set specification or a single product launch. Emmanuel Till-Vattier, the company’s vice president of sales for EMEA, discussed making migration from Arm to RISC-V easier, customizing processors, functional safety, and cybersecurity. The RISC-V International account was published on May 15, 2025; its short summary is useful for understanding the company’s message, but it does not provide benchmarks, pricing, customer deployment data, or detailed certification scope. RISC-V International’s event report and Design & Reuse’s coverage provide the event context.
The central proposition is to start with a RISC-V processor baseline and adapt it for a product’s workload and requirements, while offering safety-oriented engineering materials and security mechanisms. Each part is a separate design and procurement question: customization affects hardware and software, safety relates to hazards and failures, and security includes distinct mechanisms such as secure boot and CHERI memory protection.
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RISC-V is an open, standardized instruction-set architecture. That openness lets vendors build different processor implementations that execute RISC-V software, but it does not make every vendor’s implementation, design tools, support, or license free. Codasip sells processor IP and design automation; its processor portfolio and architecture-license description distinguish conventional processor licensing from a deeper customization relationship.
#1 Best Overall
- Flexible MCU Board: Incorporate the ESP32-C3 32-bit RISC-V chip, operating up to 160 MHz, mounted multiple development ports,
- Developer Friendly: Compatible with Arduino IDE, MicroPython, CircuitPython, PlatformIO, ESP IDF, Zephyr, Matter, ESPNow, Meshtastic, WLED, ESPHome, Home Assistant, Ubidots
- Outstanding RF performance: Complete Wi-Fi functions and Bluetooth Low Energy, while supporting communication over 100m with anFL antenna
- Elaborate Power Design: 4 working modes as low as 44 μA in deep sleep mode, while supporting lithium battery charge management
- Thumb-sized Design: 21 x 17.5mm, Seeed Studio XIAO series classic form factor
Codasip describes designing its processors in Codasip Studio using CodAL, its processor architecture description language. In its stated flow, a customer can start from a RISC-V core delivered as CodAL source, modify it, and generate hardware and software deliverables. The practical levels of control are:
- Configuration: Choose among supported architectural or implementation options without redesigning the processor.
- Bounded customization: Add custom instructions within defined limits while retaining the baseline design’s intended behavior.
- Architecture licensing: Gain broader ability to change the processor architecture and microarchitecture using CodAL and Studio.
The exact rights, deliverables, and permitted changes depend on the license. An RTL processor-IP license is not the same as access to a full architecture description or the tools to regenerate a design. Companies should establish who owns custom instruction definitions and generated artifacts, which tools are licensed, and what support applies to modified designs.
Why add custom instructions?
A workload-specific instruction can combine operations that software would otherwise express as several instructions. In suitable workloads—such as signal processing, compression, cryptography, or AI—it may improve performance, energy use, or area (PPA), or reduce the need for a separate accelerator. Whether it does so depends on the workload, implementation, and silicon process; automation cannot guarantee a better result for every design.
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- CH32V003 Development Minimum System Board for Nano RISC-V CH32V003F4U6 Chip TYPE-C USB 22Pin
- on-board 24MHz Crystal oscillator
- Power by TYPE-C USB
Specialized hardware also creates software and verification obligations. The compiler, debugger, simulator, verification environment, and software libraries must understand the extensions. Teams must test and maintain those components, consider binary compatibility across core configurations, and plan for future processor revisions. A standard RISC-V ISA does not make binaries using proprietary custom instructions portable to every RISC-V processor.
The L150: a concrete embedded example
The L150 was the clearest embedded example associated with the 2025 message. Contemporaneous industry coverage described its early-May 2025 launch as a low-power, area-efficient, three-stage, 32-bit RISC-V processor for real-time embedded applications. Codasip’s L150 product page describes configurable local memories and instruction caches, an optional small floating-point unit using the RISC-V Zfinx extension, and customization through Codasip Studio Fusion. Codasip also published an L150 product brief.
That positioning may suit a company integrating a CPU into its own microcontroller or SoC, particularly if its workload could benefit from tailored DSP or AI operations. The L150 is processor IP, not a retail microcontroller, ready-made chip, or evaluation board. The cited public material does not establish a clock speed, silicon process, benchmark score, price, or customer deployment, and it does not say that the L150 includes CHERI. Treat it as a licensable design to evaluate, not as production silicon a buyer can simply plug into a board.
Rank #3
- The ESP32-C3 SUPERMINI is positioned as a high-performance, low-power, cost-effective IoT mini development board, suitable for low-power IoT applications and wireless wearable applications
- It is equipped with a rich set of interfaces, including 11 digital I/Os that can be used as PWM pins and 4 analog I/Os that can be used as ADC pins.
- It supports four serial interfaces, including UART, I2C, and SPI.
- The ESP32-C3 features a 32-bit RISC-V CPU, including an FPU (Floating Point Unit) capable of 32-bit single-precision
- Package: 2PCS ESP32-C3 MINI Development Board ESP32 SuperMini ESP32 C3 WiFi Module
Safety, cybersecurity and memory safety are different
“Safe” and “secure” are not interchangeable. Functional safety concerns accidental faults and systematic errors that could create hazardous behavior. Cybersecurity concerns deliberate attacks. Memory safety is a specific security concern: preventing software from using invalid pointers or accessing memory beyond its authority. The mechanisms and evidence needed for each differ.
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| Area | Main concern | Relevant mechanisms | Codasip context |
|---|---|---|---|
| Functional safety | Accidental faults or systematic errors that could cause harm | Requirements traceability, diagnostics, verification, safety documentation and assessment | Codasip cites ISO 26262-related development and product claims for relevant offerings. |
| Cybersecurity | Deliberate compromise of hardware, firmware or system behavior | Secure boot, protected debug, authentication, cryptographic support and security engineering | Codasip describes security features and ISO/SAE 21434-related process positioning. |
| Memory safety | Invalid memory access or excessive pointer authority | Bounds and permissions, capability-based access control, software compartmentalization | Codasip’s CHERI-oriented work includes the X730 processor. |
| Software isolation | One component gaining unintended access to another component’s data or functions | Privilege controls, MMU or MPU boundaries, compartments and capability enforcement | CHERI is intended to strengthen compartmentalization; it does not replace system security design. |
Codasip says the L150’s development process was audited and certified by TÜV SÜD in accordance with ISO 26262 and ISO/SAE 21434. This is a claim about the relevant development process, not automatic certification of a customer’s complete SoC or end product. Before relying on it, a buyer should establish the certificate’s scope, the applicable safety integrity level, which product and deliverables it covers, and what safety manuals, analysis data, diagnostic features, traceability, and verification evidence are supplied. The customer still has system-level hazard analysis, integration, verification, and certification responsibilities. Codasip’s safety and security overview sets out its broader positioning.
Similarly, secure boot protects the chain that starts a system, while debug protection limits certain forms of invasive access and cryptographic mechanisms can protect keys or communications. None of those mechanisms is synonymous with CHERI. A secure boot chain does not establish functional safety, and a safety-oriented development process does not demonstrate resistance to every cyberattack.
Rank #4
- ESP32-C6 WiFi 6 microcontroller development board adopts ESP32-C6-WROOM-1-N8 module, which is equipped with RISC-V 32-bit single-core processor, up to 160MHz main frequency, built-in 8MB Flash
- Integrates WiFi 6, Bluetooth 5 and and IEEE 802.15.4 (Zigbee 3.0 and Thread) wireless communication, with superior RF performance
- Integrates rich peripherals including SPI, UART, I2C, I2S, LED PWM, SDIO and other interfaces, compatible with the pinout of ESP32-C6-DevKitC-1-N8 development board, more convenient to use and expand a variety of peripheral modules
- Onboard CH343 and CH334 USB HUB chips, supports USB and UART development at the same time via a USB-C port
- Comes with online examples and tutorials for ESP-IDF development environment
CHERI, the X730 and the software implications
CHERI—Capability Hardware Enhanced RISC Instructions—uses hardware-enforced capabilities to constrain what pointers can access. A capability carries authority, including bounds and permissions, so software can be organized into compartments with restricted access. The aim is to mitigate classes of memory-safety vulnerabilities and limit the damage when a component is compromised. It is not a substitute for authentication, key management, supply-chain security, protection from every side channel, or correct application logic.
Codasip describes its X730 as a 64-bit RISC-V application processor implementing CHERI-RISC-V and calls it the first commercially licensable processor of that kind. Its product page specifies an in-order, nine-stage, dual-issue design with capability-aware register and memory-system changes. Codasip also claims an area increase of less than 5% compared with the corresponding A730 baseline. These are vendor-published descriptions and a vendor comparison, not independently verified benchmark results or a guarantee for every implementation. See the X730 product description for the company’s specifications.
Codasip’s X730 page lists a CHERI software stack that includes LLVM 17-based tools, QEMU, OpenSBI, U-Boot, Linux 6.10, FreeRTOS, GDB, Yocto, and BusyBox. Those are the versions and components stated on that page; they should not be read as a guarantee that every application, driver, library, or production workflow is ready for a particular buyer. A team should test its language and compiler needs, third-party dependencies, debug process, operating-system support, workload performance, and long-term security maintenance.
Best Value
- Ample PSRAM Storage – The development board offers 8MB PSRAM, providing substantial extra memory for handling more complex tasks, large data buffers, and advanced processing.
- Enhanced Multi-Tasking Capability – With the additional 8MB PSRAM, the ESP32-C5-WIFI6-KIT can efficiently manage multiple protocol stacks simultaneously, ensuring smooth operation in multi-tasking IoT environments.
- Support for Medium-Load Applications – The 8MB PSRAM allows the ESP32-C5 to handle medium-load applications more effectively, making it ideal for scenarios requiring real-time data processing or continuous communication.
- Seamless Performance – The increased memory improves the overall performance and responsiveness of the device, particularly when running applications with larger memory footprints or more demanding computations.
- Future-Proof for Complex Projects – With 8MB of PSRAM, developers are better equipped to build scalable, high-performance solutions that support both current and future IoT use cases, offering flexibility for future-proofing designs.
Codasip Prime is presented as an FPGA-based CHERI exploration platform. Codasip says it includes an X730 processor, system and peripheral IP, security IP, CHERI tag-management hardware, Linux, a debug probe, and CHERI software-development tools. That makes it an evaluation path for teams that need to explore hardware and software before a silicon commitment; it is not simply a low-cost general-purpose RISC-V development board.
Independent reader supportYour contribution helps us test, update, and keep practical guides available for everyone.Codasip’s broader portfolio—and the 2026 change
Codasip’s processor overview groups its offerings into embedded, high-performance embedded, 64-bit application, and CHERI-enabled processors. Its application-processor page describes 64-bit cores with MMUs and Linux support, multicore options up to four cores, L1 instruction and data caches, and L2 cache coherence. These are portfolio descriptions, not a promise that every listed configuration is available under every license or in every market.
On April 8, 2026, Codasip announced a strategic pivot toward cyber-resilient semiconductor architectures, CHERI processors, CHERI SoCs, and CHERI FPGAs, as well as a planned divestiture of its low-end RISC-V processor business and a broad Studio license for the acquiring company. The announcement said the transaction was expected to close in approximately a month; the cited material does not independently confirm that it closed. As a result, the 2025 “custom, safe and secure” message is best understood as the foundation of a strategy that later became more focused on security, not a definitive account of Codasip’s current portfolio. Buyers should confirm the owner, licensing route, roadmap, and support arrangements for any product affected by the announced transaction. Codasip’s announcement describes the planned change.
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Who should evaluate Codasip?
Codasip is most relevant to companies building a custom SoC that need more control than a fixed processor baseline, or that have a specific reason to evaluate safety collateral or CHERI-based memory protection. It is a less natural fit for a buyer seeking an inexpensive, ready-to-use microcontroller or immediate drop-in replacement for an Arm chip. Arm software binaries do not become compatible merely because the destination processor implements RISC-V; migration still involves software, toolchain, verification, and system work.
Before starting a commercial evaluation, engineering and procurement teams should resolve these questions:
- Does the workload need RV32 or RV64, Linux and an MMU, real-time behavior, caches, tightly coupled memory, floating point, multicore, or a dedicated accelerator?
- Would supported configuration be enough, or is custom instruction or full architecture access necessary? What engineering work will compiler, debugger, simulator, ABI, and verification support require?
- Which exact deliverables and rights come with the proposed license: RTL, CodAL source, Studio access, generated SDK, verification collateral, safety documents, or support for customer modifications?
- For safety use, what product and process scope is covered, what safety level is applicable, and what evidence and integration work remain with the customer?
- For security use, does the threat model call for secure boot, protected debug, cryptographic support, memory-safety enforcement, or several of these? Can the existing software stack accommodate CHERI?
- What are the license fees, royalties, support terms, customization costs, and roadmap commitments? Public prices for Codasip processor licenses, Studio, L150, X730, and Codasip Prime are not stated in the cited product material.
- Given the announced low-end business divestiture, who will license and support the specific product through the intended product lifecycle?
The right comparison is not simply “RISC-V versus Arm.” It is the complete cost and risk of the chosen processor, tools, software migration, verification, safety evidence, security model, and long-term support against the requirements of the intended system.
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