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At Hot Chips 2025, Celestial AI presented a Photonic Fabric Module that uses optical links to connect compute, memory and switching resources in an AI system. Its notable packaging idea is to place optical connectivity within the package footprint—not only along its outer edge—to ease the I/O limits of large multi-chip designs. The presentation outlined a Gen1 architecture and vendor-stated specifications; it did not independently establish production performance or commercial availability.
What Celestial AI showed
Celestial AI’s Hot Chips presentation described a photonic-interposer-based fabric for moving data among accelerator resources and memory. The package concept combines electronic and photonic components with HBM, DDR5 memory and switching. ServeTheHome’s coverage, published August 26, 2025, included a visual walkthrough and a physical module or representative package.
This is not an optical processor or “optical memory.” Electronic logic and memory remain central. The proposed change is to how data travels between chiplets and memory: photonic links supplement or replace some electrical package connections. The module is a building block; the Photonic Fabric Switch/Appliance is the system-level component intended to connect resources across the fabric.
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The packaging problem: limited I/O beachfront
Large accelerators can combine multiple compute dies and memory stacks, all of which need high-bandwidth connections. Electrical traces and bumps must fit within a package’s routing and power limits. The package edge—the “silicon beachfront” available for connections to other components—does not grow as quickly as the amount of compute and memory that may need to communicate.
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Celestial AI’s thesis is that optical connections can be routed through an interposer or module and placed toward the package interior, rather than being limited to the perimeter. In principle, this gives designers more freedom to position chiplets and memory while reducing reliance on long, high-speed electrical paths. That is a packaging and data-movement proposal, not proof that every electrical link can or should become optical.
| Approach | Typical connection location | Key design pressure |
|---|---|---|
| Electrical chiplet links | Across the package, substrate or interposer | Electrical loss, routing density, reach and power |
| Conventional co-packaged optics (CPO) | Optical engines generally near the package edge | Perimeter space and fiber/engine placement |
| Celestial AI Photonic Fabric concept | Optical connectivity through the package or interposer, including interior placement | Photonic packaging, assembly, thermal design and test |
This comparison summarizes the architectural positioning described by Celestial AI and ServeTheHome; implementations vary, and CPO is a broad category rather than one fixed layout.
How the Gen1 memory and fabric are described
The Hot Chips 2025 presentation describes an in-network shared-memory system. Its Gen1 design pairs HBM with DDR5 capacity and optical interconnect components. The slides describe HBM as a write-through cache for DDR and also list hardware semaphores.
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|---|---|
| HBM capacity per module | 48–72 GB |
| DDR capacity per module | 2 TB |
| Module bandwidth | 7.2 Tb/s, full duplex |
| Latency | Approximately 200 ns; the cited coverage does not establish an application-visible end-to-end measurement path |
| Switch/appliance | 256 channels and 16 concurrent ports |
| Memory behavior | HBM described as a write-through cache for DDR; hardware semaphores included |
These are presentation specifications, not independent benchmarks. Full duplex means traffic is specified in both directions; it does not, by itself, show sustained application payload bandwidth. The stated 7.2 Tb/s should not be read as guaranteed workload throughput, nor should the approximately 200 ns figure be compared directly with local GPU HBM latency without knowing the access path and measurement conditions.
There is also a small accounting discrepancy in published summaries. The Hot Chips slide lists 2 TB of DDR plus 48–72 GB of HBM, while an IEEE Communications Society summary describes approximately 2.07 TB total memory. The available sources do not fully explain whether this reflects rounding or a particular configuration, so the figures should not be silently treated as an exact, universal total.
What the component names mean
- PFLink: Celestial AI’s name for its Photonic Fabric link technology, intended to connect chiplets and accelerator or memory resources.
- EIC: Electronic integrated circuit, responsible for electrical interface and signal-processing functions.
- PIC: Photonic integrated circuit, which carries out optical functions.
- OIMB: Optical multichip interconnect bridge, the photonic bridge or interposer element used to connect chiplets optically.
- OMAC: Optical MAC. ServeTheHome connected this term to reliability, availability and serviceability (RAS) functions.
- CPO: Co-packaged optics, a general approach that integrates optical engines near a switch or compute ASIC.
ServeTheHome also reported that Celestial AI discussed matching SerDes to the channel for power efficiency and an optical MAC for RAS. Those are reported company design claims, not independently verified operating results.
EAM modulation and the manufacturing trade-off
Celestial AI presented electro-absorption modulators (EAMs), rather than the ring modulators common in some silicon-photonics designs. A ring modulator uses a resonant structure to affect light and can require careful temperature and wavelength control. An EAM changes how much light passes through by changing absorption.
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Celestial AI positioned EAMs as favorable from a thermal standpoint, but that is a design trade-off, not a universal verdict. Drive voltage, insertion loss, laser efficiency, wavelength stability, fabrication and manufacturability also matter. The cited event coverage does not provide comparative measurements that would establish one modulator type as superior in all systems.
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- Supports 800Gbps optical transmission, delivering high bandwidth connectivity for AI computing clusters, cloud networks, and enterprise data centers.
- Integrated with SiPh technology to improve optical performance, reduce power consumption, and support next-generation data center upgrades.
- Designed for longer-reach optical networking, supporting up to 2km single-mode fiber transmission, suitable for data center interconnection.
- Uses 2x400G FR4 architecture, enabling flexible deployment in modern Ethernet networks and supporting high-density switch environments.
- Provides excellent signal integrity, low latency transmission, and reliable operation for mission-critical AI and cloud applications.
Moving optical interfaces into a package also raises practical manufacturing demands. Optical surfaces and coupling must survive assembly, contamination control, alignment tolerances, mechanical stress and thermal cycling. ServeTheHome identified protecting optical interfaces during manufacturing as a challenge and reported Celestial AI’s claim that its packaging technology addresses it. Production yield and long-term reliability are not established by a presentation or a physical example.
Independent reader supportYour contribution helps us test, update, and keep practical guides available for everyone.How it differs from other interconnect options
The proposed distinction from conventional CPO is placement and topology: Celestial AI emphasizes optical links within the package/interposer arrangement, including interior locations, rather than focusing only on optical engines around the edge for external network links. The potential benefit is more flexible chiplet connectivity and less dependence on package perimeter. The cost is a more complex photonic package to assemble, cool, test and service.
It is not a direct substitute for every electrical scale-up fabric, CXL memory system or network switch. Electrical fabrics may be more mature and simpler to integrate, though reach, loss and power can constrain scaling. CXL offers a standards-oriented path to memory expansion and sharing, but its topology and performance are not automatically equivalent to an in-package photonic fabric. Adding local HBM remains simpler when capacity, package area, thermal budget and cost allow it.
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Other optical-interconnect efforts, including Lightmatter Passage and Ayar Labs’ optical connectivity work, are relevant architectural context, not interchangeable products. Comparisons need to specify the layer at issue—package topology, protocol, memory semantics, reach, latency, bandwidth or energy.
What is demonstrated—and what remains open
The available event material establishes that Celestial AI presented a Gen1 architecture and specifications at Hot Chips 2025, and that ServeTheHome showed physical package/module material. ServeTheHome also reported the company’s statement that it had completed four tapeouts. Tapeouts indicate design activity and silicon iteration; they do not establish production readiness, customer qualification or shipment.
The cited sources do not independently demonstrate sustained bandwidth on AI workloads, tail latency under contention, energy per delivered bit, production volume, field reliability, package yield, software maturity, cost or deployment with specific commercial accelerators. Nor do they fully specify how the shared-memory model appears to software.
For a system architect, the most consequential unanswered questions are how HBM cache hits and misses are handled; whether cache management is hardware-, software- or hybrid-controlled; what coherency, ordering and atomic-operation semantics are provided; how multiple accelerators share data; and what drivers, runtimes and libraries are required. Engineers would also need workload-level evidence for sustained payload bandwidth and latency, link recovery and error handling, serviceability, power, manufacturing economics and interoperability.
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1Repair Windows errors before they cause bigger problems2Fix the driver behind crashes, sound loss and screen glitches3Clear out junk files and repair common Windows errorsUntil those details are public and validated, Photonic Fabric is best understood as a promising packaging and fabric architecture rather than a proven drop-in memory or accelerator upgrade. Its value will depend on whether the optical package can be manufactured reliably and whether the complete system—not just its link specification—delivers useful performance with workable software and economics.
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