Some links on this page are affiliate links: if you buy through them we may earn a commission, at no extra cost to you.
Integrated capacitors are built from conductive layers, transistor gates, or semiconductor junctions already available in a chip process. Their practical value depends on more than nominal capacitance: area, voltage dependence, leakage, loss, and process-specific limits all matter. A representative example in the Analog Devices-labeled textbook chapter hosted by All About Circuits uses about 2 fF/µm²: an idealized 50 µm × 50 µm plate would provide roughly 5 pF. That density is illustrative, not a universal specification; the foundry’s PDK determines which capacitor structures are available and how they behave.
Why useful capacitors take space on a chip
A capacitor needs two conductive plates separated by an insulator. IC processes contain many insulating layers, but ordinary interlayer oxides are primarily designed to isolate conductors and limit unwanted coupling—not to provide high intentional capacitance in a compact area. A useful capacitor may therefore use a dedicated dielectric stack, a transistor gate dielectric, or a reverse-biased semiconductor junction.
For a parallel-plate structure, the first-order relationship is C ≈ εA/d, where C is capacitance, ε is dielectric permittivity, A is plate area, and d is dielectric thickness. A thinner dielectric or larger plate area increases capacitance. Thin dielectrics can bring lower voltage limits and tighter reliability constraints; increasing area consumes die space and can add parasitic coupling. A process-specific capacitor option may also require an additional mask or process module.
Free tools Windows power users keep installed
One-click scans. No signup required.
The textbook chapter gives approximately 2 fF/µm² as a representative density and calculates about 5 pF for a 50 µm × 50 µm capacitor. The example illustrates why even a few picofarads can be significant on a die; it should not be treated as a modern-process guarantee. All About Circuits’ chapter on capacitors in IC processes discusses the example and its process-dependent context.
#1 Best Overall
- 24 Values, 480pcs Total: Includes 20pcs of each value (10pF, 22pF, 30pF, 47pF, 100pF, 220pF, 330pF, 470pF, 1nF, 2.2nF, 3.3nF, 4.7nF, 6.8nF, 10nF, 22nF, 47nF, 68nF, 100nF, 220nF, 470nF, 1uF, 2.2uF, 4.7uF, 10uF), covering a wide range for diverse electronics projects.
- Premium Quality & Durability: Multilayer monolithic ceramic capacitors with 50V withstand voltage, ±10% tolerance, and epoxy resin coating for humidity resistance and long-term reliability.
- Organized Storage Box: Compact re-sealable plastic case with labeled compartments to prevent mixing and ensure easy access. Ideal for hobbyists and engineers.
- Versatile Applications: Perfect for bypass circuits, filtering, signal coupling, DIY electronics, industrial control systems, and electron experiments.
- Clear Markings & Easy Identification: Each capacitor features printed capacitance codes (e.g., 104=100nF=0.1uF), simplifying component selection during assembly.
How integrated capacitor structures differ
Foundries use different names and layer stacks. MIM, MOM, poly-poly, MOS, junction, and varactor are common terms, but they do not identify one universal construction or performance level. The PDK is the authority for the actual terminals, models, design rules, and ratings.
Dedicated dielectric capacitors
A process may provide a designated capacitor region with a dielectric and electrode stack optimized for intentional capacitance. The chapter describes a mask-defined thinner oxide or nitride region as one way to increase density. Other processes offer structures such as metal-insulator-metal (MIM), metal-oxide-metal or interdigitated metal (MOM), or poly-poly capacitors. Their exact construction varies by foundry.
A characterized dedicated structure can be a good candidate when predictable capacitance or linearity matters, but no label guarantees a particular density, voltage rating, loss, leakage, or cost. Check the PDK model and process options rather than assuming every flow includes the same capacitor module.
Rank #2
- 10pf - 10uf 30 value 300 pcs capacitor set, 30 individual compartment
- Each compartment has a plastic cover/door that opens and closes with a nice positive snap.
- 🟡 10pf 15pf 22pf 33pf 47pf 68pf 100pf 220pf 470pf 680pf
- 🔵 1nf 2.5nf 2.2nf 3.3nf 4.7nf 6.8nf 10nf 22nf 47nf 68nf
- 🔴 0.1uf 0.15uf 0.22uf 0.33uf 0.47uf 0.68uf 1uf 2.2uf 4.7uf 10uf
MOS capacitors
A MOS capacitor uses a transistor gate as one electrode and the channel or source/drain region as the other. Its capacitance depends on the gate bias because the semiconductor beneath the gate changes state. Depending on substrate type and bias, the surface moves among accumulation, depletion, and inversion. In inversion, a channel forms; the chapter’s NMOS example emphasizes that gate capacitance changes significantly once gate voltage exceeds threshold. Gate-to-source/drain overlap capacitance may remain even when an inversion channel is absent.
MOS structures can offer high capacitance density in some processes, but their voltage-dependent capacitance can cause gain error or distortion when the signal swing is large. Use a bias-dependent model at the intended DC operating point and signal amplitude. The usable voltage range is constrained by the gate dielectric’s reliability and the device rating. The chapter provides a qualitative explanation, not a complete C–V model or universal leakage, Q, or layout specification.
Junction capacitors
A reverse-biased PN junction has a depletion region that contributes to its effective capacitance. Increasing reverse bias widens that region, so capacitance falls. The chapter describes junction capacitance as voltage-dependent but less so than the MOS gate capacitance in its comparison. A junction already present in a process can sometimes be used without a capacitor-specific mask, although its suitability depends on the device structure and rules.
Rank #3
- BOJACK High Quality Multilayer Monolithic Ceramic Capacitor Assortment Kit.
- Capacitance Model: 10 Type--(0.1uF, 0.15uF, 0.22uF, 0.33uF, 0.47uF, 0.68uF, 1uF,2.2uF, 4.7uF,10uF)
- Capacitors tolerance: ±10%
- Package Quantity: 300 pcs (Each model 30 pcs), Packed in A Rugged Convenient Re-sealable Plastic Storage Case.
- Excellent Humidity Resistance, Miniature Size, Wide Capacitance, Reliable Performance. Wide Applications in Computers, Data Processing, Telecommunication, Industrial Control, etc.
Junction type matters. The chapter notes that collector-base capacitance can compete with oxide capacitance per unit area in its process context, and that base-emitter capacitance can be higher there, with breakdown around 6 V in the described example. That figure is specific to the example; it is not a general rating for bipolar, CMOS, or high-voltage processes. Leakage, polarity, substrate coupling, and breakdown must be checked for the chosen device.
Varactors and other process terms
A varactor is a capacitor intended to vary with voltage, commonly implemented using a junction or MOS structure. It can be useful for tuning an oscillator or resonant circuit, where voltage dependence is the purpose rather than an error. Poly-poly and MIM identify broad electrode/dielectric arrangements; MOM often describes capacitance formed between patterned metal features. The PDK defines the precise implementation and its qualified use.
Why the second plate changes behavior
One electrode is often metal or polysilicon. If the opposing electrode is semiconductor diffusion, depletion within silicon can change the effective separation and therefore the capacitance with bias. This differs from a structure in which two conductors are separated only by a fixed dielectric. A capacitor’s nominal value at one bias may not represent its effective value across another operating range. The chapter discusses this distinction for diffusion electrodes and their voltage dependence.
Rank #4
- 【 Product Name 】: High quality ceramic capacitor 50V Assortment box kit.
- 【50V Ceramic capacitor models】: 1pF, 2pF, 3pF, 4pF, 5pF, 6pF, 7pF, 8pF, 9pF, 10pF, 15pF, 18pF, 20pF, 22pF, 24pF, 25pF, 27pF, 30pF, 33pF, 36pF, 40pF, 47pF, 50pF, 56pF, 62pF, 68pF, 75pF, 82pF, 100pF, 120pF, 140pF, 150pF, 180pF, 200pF, 220pF, 270pF , 300pF, 330pF, 390pF, 470pF, 560pF, 680pF, 750pF, 820pF, 1nF, 1.5nF, 2nF, 2.2nF, 3.3nF, 4.7nF, 5.6nF, 6.8nF, 10nF, 15nF, 20nF, 22nF, 33nF, 47nF, 68nF, 100nF （A set of 60 models with 1200 pieces, each model with 20 pieces）.
- 【 Product Features 】： This ceramic capacitor combination kit has high precision, low loss, stable performance, and is suitable for students, engineers, technicians, and DIY enthusiasts to conduct experiments.
- 【Scope of Application】:Widely used in negative ion products, X-ray machines, voltage doubling modules, power equipment, igniters, etc.
- 【Transparent storage box】: Small in size, lightweight, easy to store and carry, each model is packed in a transparent bag and packaged in a sealed reusable box.
Estimate area before committing to a design
Using the chapter’s illustrative density of 2 fF/µm², an idealized active plate area is capacitance divided by density. The dimensions below assume a square and exclude layout overhead:
| Target capacitance | Approximate idealized area | Square side |
|---|---|---|
| 1 pF | 500 µm² | 22.4 µm |
| 5 pF | 2,500 µm² | 50 µm |
| 10 pF | 5,000 µm² | 70.7 µm |
| 100 pF | 50,000 µm² | 223.6 µm |
These estimates use the chapter’s representative density, not a foundry guarantee. Actual layout can require additional area for enclosure and spacing, contacts or vias, routing, shielding, guard rings, matching geometry, high-voltage clearances, and metal fill or density rules. Use the PDK’s area formula and extracted parasitics in place of this back-of-envelope estimate.
Choose for the circuit’s real operating conditions
There is no universally best integrated capacitor. Select against the actual bias, signal swing, frequency, and accuracy needs, then confirm that the process offers a qualified device for the job.
Best Value
- 10pf - 10uf 30 value 900 pcs capacitor set, 30 individual compartments
- Each compartment has a plastic cover/door that opens and closes with a nice positive snap.
- 🟡 10pf 15pf 22pf 33pf 47pf 68pf 100pf 220pf 470pf 680pf
- 🔵 1nf 2.5nf 2.2nf 3.3nf 4.7nf 6.8nf 10nf 22nf 47nf 68nf
- 🔴 0.1uf 0.15uf 0.22uf 0.33uf 0.47uf 0.68uf 1uf 2.2uf 4.7uf 10uf
| Design need | Possible direction | Principal caution |
|---|---|---|
| High linearity | Consider a PDK-qualified MIM or suitable metal/poly structure. | Area, process options, and voltage limits vary. |
| High density | Consider a MOS or dedicated high-density option. | Bias dependence and voltage limits can dominate. |
| Voltage-controlled tuning | Consider a MOS or junction varactor. | Check tuning range, nonlinearity, Q, and loss. |
| Use of an existing process structure | A junction capacitor may avoid a capacitor-specific module. | Check leakage, polarity, substrate coupling, and breakdown. |
| Precision ratios | Use a matched PDK capacitor array where available. | Layout gradients and parasitics affect matching. |
| Amplifier compensation | Choose a compact, well-modeled capacitor appropriate to the loop. | Area and loading affect settling and bandwidth. |
| RF resonance | Use a process-supported structure with suitable loss and Q. | Substrate loss, routing, and coupling can limit performance. |
For any option, distinguish nominal capacitance from small-signal capacitance at a bias, large-signal effective capacitance over a swing, and extracted capacitance including layout parasitics. Leakage is especially important for sample-and-hold nodes, integrators, charge storage, and other high-impedance circuits. At high frequency, series resistance, bottom-plate parasitics, substrate loss, and coupling to nearby conductors can matter as much as the nominal value.
Account for layout, matching, and verification
Precision analog design may depend more on ratio matching than on absolute capacitance. Matched devices are commonly laid out with symmetry, identical orientation, interdigitation or common-centroid arrangements, and dummy edges where the PDK recommends them. Routing symmetry, shielding, gradients, and mechanical or thermal context can also affect results. Use the foundry’s layout guidance rather than treating any one pattern as universally required.
- Instantiate the characterized PDK device, not just a generic schematic capacitor symbol.
- Confirm terminals, well ties, polarity, voltage class, and applicable design rules.
- Run DRC and LVS, then perform parasitic extraction on the actual layout.
- Simulate capacitance over the intended DC bias, signal amplitude, frequency, process, voltage, and temperature conditions.
- Check leakage, transient stress, reliability limits, and substrate coupling for sensitive nodes.
- Use matching structures and Monte Carlo analysis when the design depends on capacitor ratios or precision.
Why making it larger can make the circuit worse
More capacitance can consume die area and increase coupling to substrate, neighboring devices, and routing. It can also load a driver, slow settling, reduce bandwidth, lengthen startup, or increase charge injection and clock feedthrough in switched circuits. A large capacitor can be harder to match and route cleanly. If a special capacitor module is required, it may also affect process cost. These trade-offs are why an on-chip capacitor is generally chosen for functions such as compensation, filtering, sampling, timing, or tuning—not as a replacement for board-level bulk energy storage.
Do these 3 things before closing this tab:
1Clear out junk files and repair common Windows errors2Fix the driver behind crashes, sound loss and screen glitches3Repair Windows errors before they cause bigger problemsTypical uses and the role of parasitics
Intentional capacitors appear in amplifier frequency compensation, loop filters, sample-and-hold circuits, switched-capacitor filters, ADC and DAC networks, charge pumps, oscillator tuning, RF resonant networks, bootstrapping, and local decoupling. The appropriate structure depends on whether the circuit prioritizes linearity, density, matching, tuning range, or low loss.
Unintended capacitance between interconnects, devices, and substrate can sometimes be modeled or deliberately exploited, but it is not interchangeable with a characterized capacitor. Its value can be especially sensitive to layout and surroundings. Extraction is essential whenever that coupling affects stability, bandwidth, noise, or accuracy.
Further reading
The topic is part of the broader Designing Analog Chips textbook. The specific chapter is hosted on All About Circuits and labeled “Analog Devices”; that labeling alone does not establish separate current hosting on an Analog Devices website.
Quick Recap
Product prices and availability are accurate as of the date/time indicated and are subject to change. Any price and availability information displayed on Amazon at the time of purchase will apply.
Quick wins for a faster PC:
Fix the driver behind crashes, sound loss and screen glitchesFind Drivers →Repair Windows errors before they cause bigger problemsFix Now →Scan for outdated or missing drivers - takes under a minuteDriver Scan →
