Bus-hold circuitry—also called a bus keeper or weak keeper—is a feedback circuit on a CMOS input or I/O pin. When an external driver releases the line and it becomes high impedance, the keeper weakly drives the pin back to its last valid logic state. Use it to stop an otherwise floating push-pull signal from chattering; use a fixed pull-up, pull-down, or redesigned interface when the system requires a deterministic default, wired logic, or guaranteed power-state behavior.
The problem bus hold solves
A CMOS input can draw very little steady-state current, but that high impedance makes an undriven pin vulnerable. A typical sequence is:
- An external device drives the line high or low.
- The driver changes to high impedance.
- Pin capacitance temporarily preserves the old voltage.
- Leakage, noise, and the receiver threshold move the voltage into an indeterminate region.
- The input may switch repeatedly, causing false interrupts, extra power consumption, or bus chatter.
Bus hold senses the existing logic state and supplies a weak restoring current. It is a state-retention and noise-avoidance feature, not a storage element that preserves data indefinitely or through power loss. Texas Instruments describes it as an active feature for holding unused or non-driven data inputs at a valid level (TI standard-logic guidance).
How a bus keeper works
The exact transistor topology differs by device, so the following is a conceptual model rather than a universal schematic:
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weak feedback
┌─────────────────┐
External ─────┤ I/O pad ├──── Internal input buffer
bus └─────────────────┘
└── weak pull high
└── weak pull low
A sensing inverter or latch controls weak PMOS and NMOS paths. A high level enables a weak pull toward high; a low level enables a weak pull toward low. A valid external driver overrides that feedback and establishes the opposite state. The keeper is therefore not a normal push-pull output and should not be used to drive a load.
AMD/Xilinx describes the CoolRunner-II implementation as a weak keeper that monitors the pad and drives it to match the input (XAPP382). Its statement that the behavior is “equivalent to a full latch” refers to the retained electrical level at the pin—not to a clocked latch with reset, timing, or independent data storage.
Bus hold versus a fixed pull-up or pull-down
| Characteristic | Bus hold | Pull-up or pull-down |
|---|---|---|
| Selected state | Retains the last driven state | Always biases to one fixed state |
| Undriven behavior | Weakly restores the previous level | Moves toward the resistor’s rail |
| Static current | Usually low in a stable state; contention and switching can add current | Flows continuously when driven against the resistor |
| Components | May require no external resistor | Requires an external or internal bias element |
| Startup | Device-family-specific and potentially undefined | Usually predictable from the network |
| Shared wired buses | Needs keeper-current and contention analysis | Easy to model when correctly sized |
Choose bus hold when a normally push-pull line may briefly float and retaining its last state is acceptable. Choose a resistor when the line needs a known reset or power-up state, an open-drain high level, a calculated rise time, or a bias that remains effective while the keeper device is unpowered. TI generally discourages adding external pull-up or pull-down resistors to inputs that already use bus hold unless the specific datasheet permits it (TI guidance).
Reading bus-hold electrical specifications
Search the datasheet for these terms:
I_I(hold): input current associated with holding the previous state while the external driver is high impedance.IBHHandIBHL: high-state and low-state sustaining currents.IBHHO: high-state overdrive current—the current an external sink must provide to force a held high line low.IBHLO: low-state overdrive current—the current an external source must provide to force a held low line high.
Sustaining and overdrive currents are more useful for signoff than a single resistance number. Current varies with voltage, supply, process, and temperature, and source and sink behavior may not be symmetrical.
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For a first-order resistor model only:
Ikeeper ≈ ΔV / RBH
Then check the worst-case overdrive requirement against the driver’s IOL or IOH while still meeting the receiver’s VIL(max) and VIH(min). Include supply and temperature corners, all parallel keepers, and the type of driver—push-pull, open-drain, open-source, or analog.
Why keeper resistance varies so widely
There is no industry-wide bus-hold resistance. It depends on process, I/O voltage, pin architecture, logic family, device generation, and operating mode. Published examples illustrate the spread:
| Device-family example | Published value or behavior | Qualification |
|---|---|---|
| Intel/Altera Arria V | Approximate RBH of 7 kΩ |
Nominal value for the cited Arria V documentation |
| AMD/Xilinx CoolRunner-II | Approximately 100 kΩ at 1.8 V | Approximate, family- and voltage-specific value in the November 11, 2002 XAPP382 |
| Older Xilinx CPLD documentation | Values around 50 kΩ have appeared | Historical examples, not a universal specification |
These figures are not interchangeable. Use the selected part’s minimum and maximum current specifications and voltage thresholds, not a remembered “typical” resistance.
Configuration, reset, and startup behavior
Bus-hold behavior can differ between power-up, FPGA configuration, JTAG or programming mode, reset, user mode, and partial power-down. The cited Arria V documentation says bus hold becomes active only after configuration and captures the pin value present by the end of configuration (Arria V bus-hold documentation). It also states that bus hold and the programmable pull-up cannot both be enabled.
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- The pin state before configuration and during reset.
- Whether the keeper is disabled, enabled, or replaced by another bias during power-up.
- What happens if an external source drives the pin during configuration.
- Whether reset preserves the last state or reinitializes the I/O.
- Whether an external resistor is required for a guaranteed system reset state.
Do not make bus hold the sole reset-state guarantee unless the manufacturer explicitly specifies that behavior.
Shared, open-drain, and wired-logic buses
Open-drain and open-collector interfaces depend on a pull-up to create the high state after every device releases the line. A keeper can retain a low state and oppose that pull-up. On a shared reset line, NXP warns that bus-hold current can create enough voltage drop across the pull-up to make the logic level read low; its MSC8112 example uses a 1 kΩ pull-up in a reference design but cautions against making the pull-up unnecessarily small because of output-current limits (NXP AN3678).
Normally disable bus hold on I²C-like, wired-OR, interrupt, reset, and shared-alert lines unless the complete current and voltage analysis says otherwise. Sum the worst-case current of every connected keeper, verify the resulting high-level voltage, and check rise time. A keeper is not simply another harmless high-value pull-up.
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Differential, analog, and power-sensitive signals
Bus hold actively biases a pin toward its previous single-ended state, which is generally inappropriate for differential inputs. Intel/Altera explicitly requires bus hold to be disabled for differential I/O in the cited Arria V documentation (Arria V bus-hold documentation).
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Fix the driver behind crashes, sound loss and screen glitchesFind Drivers →Clear out junk files and repair common Windows errorsFree Scan →Use similar caution with ADC and comparator inputs, high-impedance sensors, analog multiplexers, transmission-line terminations, and level translators. During power-down or hot insertion, evaluate bus hold alongside Ioff, input-overvoltage tolerance, protection-diode paths, supply sequencing, and power-up three-state behavior. TI distinguishes bus hold from Ioff: the former retains an input state, while the latter specifies power-off leakage behavior (TI guidance). Bus hold alone is not a hot-plug guarantee.
Using bus hold in standard logic, CPLDs, and FPGAs
Standard logic
Some logic families identify bus-hold inputs in the feature list or part suffix. TI’s SN74LVTH540 product page lists bus hold on data inputs (TI SN74LVTH540). Confirm the exact ordering code, voltage range, Ioff, and overdrive-current limits in its datasheet.
CPLDs
CPLDs may offer bus hold as an optional I/O termination distinct from an internal pull-up. CoolRunner-II documentation is a historical example (XAPP382); do not transfer its 100 kΩ-at-1.8 V figure to current AMD devices.
FPGAs
FPGA tools may expose bus hold per pin, but availability can depend on pin type, I/O standard, configuration state, and tool version. The Arria V example documents per-pin configuration, restrictions on differential I/O, and incompatibility with programmable pull-up. Use the selected family’s current pin-assignment guide rather than assuming a universal menu path or constraint syntax.
A practical verification procedure
- Record the exact part number, package, voltage, and temperature grade.
- Open the latest official datasheet and user guide.
- Search for “bus hold,” “keeper,”
I_I(hold),IBHH,IBHL,IBHHO, andIBHLO. - Determine whether the feature is always enabled, per-pin programmable, input-only, or limited to user mode.
- Read power-up, reset, configuration, power-down, and hot-socket sections.
- Define the required default state and compare it with state-retention behavior.
- Calculate worst-case keeper current and compare it with driver source and sink capability.
- Verify
VIL,VIH, rise time, and aggregate current for every shared device. - Simulate or measure driver release, opposite-state takeover, reset, configuration, and power sequencing.
- Disable bus hold or add an external bias if the measured behavior conflicts with the protocol.
Troubleshooting symptoms
The line will not switch high
Check for a keeper holding low, multiple opposing keepers, an undersized open-drain pull-up, or insufficient source current. Compare the measured voltage with VIH(min) and the specified IBHLO.
Reset remains asserted
Inspect every receiver on the reset net, the pull-up value, and the keeper state after release. NXP’s shared-reset warning is a useful failure model, not a universal resistor recommendation (NXP AN3678).
Unexpected current appears
Look for contention between a keeper and an active driver, a resistor bias, or a powered-down device. Check power-off leakage and back-power paths separately from bus-hold specifications.
The FPGA pin behaves differently before and after configuration
Compare the documented configuration-state I/O behavior with user-mode settings. A keeper that activates only after configuration cannot guarantee the earlier state.
A bus reads intermittently
Measure the released-line voltage and noise margin, then check whether the keeper is enabled on a shared or analog net where it should be disabled.
Design decision checklist
- Is the line normally push-pull and only temporarily undriven?
- Is retaining the last state actually the desired behavior?
- Can every intended driver overcome the worst-case keeper current?
- Are
VIL,VIH, timing, temperature, and supply corners satisfied? - Are multiple keepers, pull resistors, or analog loads connected?
- Does the pin need a defined state before configuration or during reset?
- Is the signal differential, analog, open-drain, wired-OR, or power-sensitive?
- Are power-down, hot-plug, and
Ioffrequirements independently met?
Conclusion
A bus keeper is a deliberately weak feedback driver that prevents a released CMOS input from floating. Its value is convenience and state retention, not universal biasing. Enable it when the last driven state is acceptable and the part’s overdrive, startup, and power behavior are documented. Disable it—or use a calculated external bias—when the interface needs a fixed default, wired logic, differential or analog operation, guaranteed pre-configuration behavior, or predictable power sequencing.
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