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AMD’s ISSCC 2023 presentation revealed the clearest public look yet at the 6nm client I/O die (cIOD) used by Ryzen 7000 desktop processors. The die shot confirms two GMI3 links for Zen 4 CPU chiplets, four 40-bit DDR5 interfaces, 28 PCIe 5.0 lanes and a small RDNA 2 graphics block.
Its most important implication is architectural: this Ryzen client I/O die is built to connect two eight-core CCDs, establishing the physical basis for the mainstream Zen 4 desktop platform’s 16-core ceiling. It also shows that display, video, audio and platform-I/O circuitry occupy far more silicon than the integrated GPU’s single compute block alone would suggest.
What AMD revealed at ISSCC 2023
AMD’s presentation at the 2023 International Solid-State Circuits Conference included a die image of the Zen 4 client I/O die. The underlying slide came from AMD; the detailed public annotation was later produced by chip analyst Locuza and discussed by HotHardware and ScreenHacker.
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That distinction matters. AMD had already disclosed the broad capabilities of Ryzen 7000’s platform, but the floorplan makes the physical organization easier to understand. It also provides evidence for conclusions that product diagrams alone could not establish, particularly the number of CPU-chiplet connections.
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- Cooler not included
CCD, cIOD and IOD: the terminology
- CCD: a Core Complex Die containing Zen 4 CPU cores and cache.
- cIOD: the client I/O die used by Ryzen 7000 desktop processors.
- IOD: a general term for AMD I/O dies. It can describe both the compact desktop cIOD and the much larger server IOD used by EPYC.
- Die shot: an image or representation of the silicon die. In this case, AMD supplied the presentation image rather than an enthusiast micrograph being the sole source.
Reading the annotated floorplan
The cIOD is not a second CPU chiplet. It is the platform hub: CPU chiplets connect to it, and it handles memory, expansion, display output, media, USB and other system-level functions.
The external annotation identifies or interprets regions associated with:
- Two GMI3 die-to-die interfaces for the CPU CCDs
- DDR5 physical interfaces and memory-controller logic
- PCI Express 5.0 connectivity
- Infinity Fabric and internal interconnect circuitry
- A small RDNA 2 graphics block
- Display-control logic
- AMD’s VCN video codec hardware
- Audio-related processing
- USB and other platform I/O
- Power-management and miscellaneous control logic
The image is informative, but not every label should be treated as an official AMD block name. Locuza’s interpretation uses visual repetition, interface placement, comparisons with earlier AMD designs and publicly known platform diagrams. Labels that are not explicitly identified by AMD are therefore best understood as expert analysis rather than formal confirmation of every internal boundary.
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Two GMI3 links explain the 16-core desktop limit
The most consequential feature in the image is the presence of two GMI3 interfaces. GMI3 is the die-to-die connection used to link Zen 4 CCDs to the I/O die.
With one standard Zen 4 CCD containing up to eight cores, two CCD connections provide the familiar maximum of 16 cores for mainstream Ryzen 7000 desktop processors. This is more than a product-stack decision: the disclosed cIOD’s physical connection scheme is designed around two CPU chiplets.
That finding also makes earlier speculation about a three-CCD Ryzen processor using the same client IOD implausible. A three-CCD package would require a different I/O die with additional links, or a substantially revised connection and package design. It could also require changes to power delivery, firmware and interconnect bandwidth.
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The conclusion must be scoped correctly. The two-port limit applies to this Ryzen client Zen 4 cIOD; it does not mean Zen 4 as an architecture can never connect more than two CCDs. AMD’s EPYC Genoa platform uses a different server I/O die designed for many more chiplets.
Four 40-bit DDR5 interfaces: dual-channel memory with ECC width
The cIOD contains four 40-bit DDR5 interfaces. A conventional DDR5 channel has a 32-bit data path, while the additional 8 bits provide the width associated with ECC-related data.
In practical desktop terminology, these four interfaces correspond to two standard 64-bit memory channels when the ECC extensions are included. That is why AM5 is generally described as a dual-channel DDR5 platform rather than a four-channel desktop design.
The silicon-level interface width should not be confused with guaranteed server-style ECC operation on every AM5 system. Actual behavior depends on several layers:
- Whether the processor supports the relevant ECC operation
- How the motherboard wires the memory subsystem
- Firmware enablement and reporting
- How the operating system exposes corrected errors
Consequently, the die shot indicates ECC-related capability in the memory interface, but it does not prove that every Ryzen 7000 motherboard provides full, usable ECC protection.
What 28 PCIe 5.0 lanes means for AM5
The Zen 4 client IOD indicates 28 PCIe 5.0 lanes. This is an on-die connectivity figure, not a promise that every AM5 motherboard exposes 28 independent expansion lanes to the user.
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- Cooler not included
Motherboard designers allocate processor connectivity among the primary graphics slot, NVMe storage, chipset links, additional slots and other platform functions. Board layout, bifurcation support, disabled ports and vendor choices determine what is available on a particular product.
The figure is also notable in comparison with earlier AMD I/O designs. Some previous client I/O dies contained 32 lanes physically but activated only 28 in the relevant configuration. The Zen 4 cIOD appears to implement 28 lanes directly, suggesting a more tightly optimized client design with less unused circuitry.
For platform context, see the contemporary report on the AMD presentation and PCIe configuration from ITHome.
The integrated GPU is small, but the graphics region is not
Ryzen 7000’s cIOD includes a minimal RDNA 2 graphics implementation. The annotated floorplan identifies one Workgroup Processor, or WGP. Under AMD’s usual organization, that is commonly described as 128 stream processors.
This is a basic display and diagnostic GPU, not a gaming-class APU. Its practical jobs include producing a display signal without a discrete graphics card, enabling basic desktop use, supporting troubleshooting and assisting with media playback.
Calling it “128 GPU cores” would be misleading. A WGP is an architectural grouping, and the cIOD’s single WGP is vastly smaller than the graphics resources in AMD’s larger APU designs. It should not be treated as equivalent to 128 full modern GPU compute units.
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- For the state-of-the-art Socket AM5 platform, can support PCIe 5.0 on select motherboards
- Cooler not included
At the same time, the WGP itself is only part of the graphics and media subsystem. The floorplan also includes a display engine, video encode/decode hardware, audio processing, clocking, power management and supporting control logic. HotHardware’s assessment is that graphics- and audio-related functions collectively occupy close to half of the die; that is a floorplan analysis, not an AMD-published percentage.
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1Clear out junk files and repair common Windows errors2Scan for outdated or missing drivers - takes under a minute3Repair Windows errors before they cause bigger problemsThis is an important chiplet-design lesson: a platform’s display and media features require substantially more silicon than shader hardware alone. The cIOD’s area reflects the complete feature set needed to boot, display an image and process media—not just the number of GPU execution resources.
Zen 4 cIOD versus Zen 3 I/O die
Zen 4’s CPU CCDs used TSMC 5nm, while the client I/O die moved to TSMC 6nm. Using a different node for the I/O die is a rational chiplet-economics decision. I/O and analog-heavy circuits do not always benefit enough from the most advanced logic process to justify consuming the most expensive wafer capacity.
Reported comparisons indicate that the Zen 4 cIOD is physically smaller than the Zen 3 desktop I/O die while carrying substantially more transistors. HotHardware cites an estimated 58% increase in transistor count. That number should be treated as a reported estimate rather than a complete, independently verified AMD disclosure for every block.
The smaller footprint is therefore not simply the automatic result of “6nm.” Die area depends on the process libraries, analog requirements, interface design, block composition and the efficiency of the layout. Zen 4’s cIOD adds DDR5, PCIe 5.0, integrated graphics and expanded media/platform functions while fitting into a compact client-oriented design.
Why the Ryzen cIOD should not be compared directly with EPYC Genoa’s IOD
Zen 4 does not use one universal I/O die across AMD’s product families. Ryzen 7000 and EPYC Genoa use different I/O implementations for different system requirements.
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| Feature | Ryzen 7000 client cIOD | EPYC Genoa server IOD |
|---|---|---|
| CCD connectivity | Two GMI3 links; designed for up to two standard CCDs | Designed to connect up to 12 CCDs |
| Memory focus | Dual-channel desktop DDR5 | Many more server DDR5 memory channels |
| Expansion | 28 PCIe 5.0 lanes in the client design | Server-class I/O and substantially greater platform connectivity |
| Graphics | Basic integrated RDNA 2 display GPU | Different server-oriented balance of I/O and platform functions |
| Primary use | Consumer desktops | Servers and data-center systems |
AMD’s Hot Chips Zen 4 EPYC material illustrates why the server IOD is much larger: it must provide the memory bandwidth, CCD connectivity, capacity and platform features required by multi-socket and data-center workloads.
Therefore, the Ryzen cIOD’s two-CCD design does not contradict EPYC Genoa’s much higher core counts. They are separate dies, packages and platform strategies.
What the die shot confirms—and what it does not
Strongly supported by the disclosure
- The image is the Zen 4 client I/O die used for the Ryzen 7000 desktop platform.
- The cIOD uses a 6nm process, while the Zen 4 CCD uses 5nm.
- Two GMI3 interfaces connect the client IOD to CPU chiplets.
- The design includes four 40-bit DDR5 interfaces, 28 PCIe 5.0 lanes and one RDNA 2 WGP.
- Display, video, audio, memory and other I/O logic occupy substantial die area.
Claims that require qualification
- “The IOD supports only 16 cores” is too broad. The disclosed client cIOD supports two standard eight-core CCDs; server and future designs can differ.
- “All Ryzen 7000 systems support ECC” is not established by the interface width. Motherboard and firmware implementation matter.
- “28 lanes means 28 user-accessible lanes” ignores motherboard routing and allocation.
- “Half the die is GPU” incorrectly combines the small WGP with the larger display, media, audio and support subsystem.
- Every annotation is official overstates the evidence. AMD supplied the die image, while detailed labels came from external analysis.
Why this matters to platform buyers
For a normal AM5 desktop, the die shot explains the platform’s balance: modern DDR5 and PCIe 5.0 connectivity, two CPU-chiplet links, basic integrated display output and a compact but feature-rich I/O hub.
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Bottom line
AMD’s Zen 4 client I/O die is the physical blueprint behind Ryzen 7000’s mainstream platform. The two GMI3 ports explain its two-CCD, 16-core configuration; the DDR5 and PCIe blocks define its AM5 connectivity; and the large graphics/media region shows how much silicon is required to provide display and media features around a very small RDNA 2 compute block.
The image is valuable not because it reveals a hidden CPU-core breakthrough, but because it makes AMD’s client-chiplet priorities visible: keep the I/O die compact and economical while adding the memory, expansion, display, media and control logic required by a modern desktop.
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