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AI chips are not abandoning round silicon wafers. The emerging change is happening mainly in advanced packaging: manufacturers are exploring large rectangular panels for assembling the increasingly large, multi-die packages used in AI accelerators and high-performance computers.
The distinction matters. Silicon dies are already generally rectangular, while the wafers used to fabricate them remain circular. The proposed “round to rectangular” shift concerns the carrier and packaging format—not an industry-wide replacement of front-end wafer fabrication.
Three shapes that are easy to confuse
“AI chips are becoming rectangular” compresses three different manufacturing geometries into one headline:
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Fix the driver behind crashes, sound loss and screen glitchesFind Drivers →Clear out junk files and repair common Windows errorsFree Scan →- Round silicon wafers: Circular wafers, commonly 300 mm at leading-edge logic and memory fabs, are used to fabricate transistors and interconnect layers.
- Rectangular dies: Individual chips are cut from those wafers. Most dies are rectangular because that shape fits circuit layouts and packages efficiently.
- Rectangular packaging panels: Large carriers or substrates used after—or partly alongside—the wafer fabrication process. They may use silicon, organic materials, glass, or engineered hybrid structures.
A panel can therefore process dies that originated on an ordinary circular wafer. Panel-level packaging does not mean that the entire chipmaking process will immediately switch to rectangular silicon.
Why AI is putting pressure on the old geometry
AI accelerators increasingly combine very large logic dies with multiple chiplets, high-bandwidth memory stacks, silicon interposers or bridges, dense die-to-die wiring, substantial package substrates, and demanding power-delivery and cooling systems.
As a result, the package is becoming nearly as important as the transistor die. A package can contain several large pieces that must be aligned, connected, tested, and kept flat across a much greater area than a conventional chip package.
That creates a geometric problem. Square or rectangular dies and interposers do not fill a circular wafer perfectly. The mismatch is most visible near the wafer edge, where unusable or difficult-to-use areas remain between the rectangular structures and the circular boundary.
EE Times, citing industry analysis, reports that Nvidia’s Blackwell architecture uses a two-reticle package and that its individual chip areas are approximately 800 mm². The same analysis estimated that roughly 64 such chips could fit geometrically on a 300-mm wafer. That is an illustration, not a production yield figure: scribe lanes, edge exclusion, test structures, die orientation, defects, and good-die yield all change the practical result.
What panel-level packaging changes
Wafer-level packaging (WLP) performs packaging operations while structures are arranged on a round wafer. Panel-level packaging (PLP) performs comparable operations on a rectangular panel, potentially allowing more package area to be processed in one cycle.
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Related technologies include:
- Fan-out PLP: Redistribution layers and package connections are formed over a panel-sized area.
- 2.5D integration: Multiple dies sit side by side on an interposer or advanced substrate.
- 3D integration: Dies or memory layers are stacked vertically using technologies such as through-silicon vias or hybrid bonding.
- Chip-on-panel-on-substrate: Dies are mounted on a panel and then integrated into a larger package or system substrate.
Panel processing already has applications beyond the largest AI processors. The AI-specific opportunity is narrower: very large, high-density packages whose dimensions make conventional wafer-format processing less attractive.
The reticle problem is separate from the wafer problem
Modern lithography tools cannot expose an arbitrarily large area in a single shot. A reticle limit is the area that can be patterned in one exposure; it is different from the total circular area available on a wafer and from the maximum practical size of the finished package.
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Large AI dies and especially large interposers may require multiple reticles, stitching, repeated exposures, and extremely precise alignment. Larger package structures also intensify yield and flatness challenges.
According to the Lam Research view reported by EE Times, an economic transition point could emerge around structures of approximately 4,500 mm², with panels becoming more attractive when reticle sizes exceed roughly 7,700 mm², potentially around 2030. These are company and industry estimates—not settled standards or guaranteed adoption dates.
Why a rectangular panel could improve economics
Better geometric utilization
A rectangular panel can match rectangular dies, interposers, redistribution layers, and package substrates more efficiently than a circular wafer. That can reduce inactive edge area, although it cannot eliminate defects, scrap, or process losses.
More package area per cycle
A larger panel could allow more package structures to pass through a process step at once. Nikon says its DSP-100 Digital Lithography System supports large substrates, including formats up to approximately 600 mm, and claims substantially higher productivity for large packages compared with 300-mm wafers. The comparison depends on package size, process flow, and the company’s measurement basis.
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Panels are potentially useful for large interposers, chiplet-based accelerators, high-density redistribution layers, and emerging glass-core or glass-carrier packages.
Potentially lower cost per good package
Lower cost is possible, not automatic. Area utilization and throughput gains can be overwhelmed by low early yields, new equipment costs, difficult handling, inspection, warpage, material expense, rework, and qualification time. The relevant metric is cost per good, qualified package—not the number of packages that fit on an empty panel.
The engineering obstacles
Warpage and deformation
Large, thin panels can bend during heating, deposition, molding, and cooling. Warpage can damage lithography overlay, die placement, bonding accuracy, planarity, and long-term reliability. Nikon’s inclusion of correction for substrate warpage and deformation illustrates that this is a central manufacturing problem.
Thermal-expansion mismatch
Glass, silicon, organic laminates, copper, mold compounds, and other materials expand at different rates. Those differences can introduce stress and alignment errors as the panel moves through repeated thermal cycles.
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New equipment and automation
Many wafer tools and factory systems are built around circular substrates. Rectangular panels may require new clamping systems, vacuum chucks, carriers, robots, alignment mechanisms, process chambers, recipes, inspection tools, and factory-control software.
Yield over a larger area
A larger panel may offer better geometric efficiency but also contains more total area in which defects can occur. A single defective region can affect a package, a group of packages, or an entire process flow. Panel economics work only if inspection, repair, process control, and yield scale with the format.
Metrology and inspection throughput
Large panels must be inspected quickly and at the required sensitivity. If inspection becomes the bottleneck, the theoretical throughput advantage disappears.
Who is developing the ecosystem?
The transition requires more than one new machine. It needs compatible materials, handling, lithography, deposition, etch, plating, molding, metrology, testing, and factory automation.
- Lam Research: Developing advanced-packaging deposition, etch, interconnect, and 3D-integration equipment for panel sizes described as ranging from approximately 300 mm to 600 mm. Lam has also introduced the Teraos 3D platform for 3D stacking and heterogeneous integration. See Lam Research and the EE Times report.
- Nikon: Its DSP-100 digital lithography system is aimed at advanced packaging on large substrates. See Nikon’s precision-equipment business.
- Applied Materials: Offers panel-processing capabilities spanning patterning, physical-vapor deposition, chemical-vapor deposition, metrology, pattern review, and testing. Its experience with large display substrates is relevant to the panel format. See Applied Materials.
- Foundries and OSATs: TSMC remains strongly associated with leading-edge AI packaging through its CoWoS family, while outsourced assembly and test companies such as ASE and Amkor are investing in increasingly sophisticated packaging. That could broaden competition, but it does not establish that TSMC is being displaced.
- Materials suppliers: Glass, silicon, organic, and hybrid carriers may all have roles. Glass is a candidate, not an inevitable winner.
Why glass is part of the discussion
Large packages need carriers and substrates with good flatness, dimensional stability, and suitable electrical properties. Glass is being considered because large glass formats can offer attractive flatness and stability, with potential benefits for signal integrity and package scaling.
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However, glass also brings mechanical, thermal, supply-chain, and manufacturability questions. The eventual market may use several materials rather than replacing silicon or organic substrates with glass everywhere. Broader forecasts that include glass substrates, fan-out packaging, or panel-processing markets may be much larger than narrower PLP estimates; market figures must therefore be compared only when their definitions match.
Independent reader supportYour contribution helps us test, update, and keep practical guides available for everyone.Timeline: an emerging transition, not a switch date
- Now: Round wafers remain central to front-end transistor fabrication, and wafer-based packaging remains dominant for many products. Panel technologies are being developed and used selectively.
- Around 2027: Lam’s forecast, as reported by EE Times, suggests panel production could begin broader industry takeoff. This is a forecast, not a universal conversion date.
- Around 2030: Larger package and reticle dimensions could make panels more economically compelling, according to Lam’s cited thresholds.
- Beyond 2030: Adoption will depend on demonstrated yield, cost per good package, customer qualification, equipment standardization, materials, and sustained AI-package demand.
A Yole Group estimate cited by EE Times placed the total panel-level-packaging market at approximately $160 million in 2024 and approximately $650 million by 2030. Those figures are a third-party forecast, not audited current revenue, and broader market definitions can produce materially different totals.
When panels make sense—and when wafers still win
| Rectangular panels become more compelling when… | Round wafers remain preferable when… |
|---|---|
| The package is large relative to a 300-mm wafer. | The process is mature and optimized for 200-mm or 300-mm wafers. |
| Most structures are rectangular and area utilization matters. | Existing equipment has high utilization and proven yield. |
| Panel throughput offsets equipment and integration costs. | The dies and packages are small enough that conversion brings little benefit. |
| Warpage and alignment can be controlled at the required pitch. | Established process control is more valuable than geometric efficiency. |
| Volume justifies dedicated panel equipment and qualification. | The package does not justify new carriers, tools, and factory automation. |
What would prove the transition is real?
Announcements about prototypes or equipment capability are important, but they do not prove high-volume adoption. Stronger evidence would include:
- A named AI customer using panel packaging in volume.
- Public production volumes and demonstrated panel yields.
- Standardized panel dimensions adopted by multiple suppliers.
- Commercial installations of lithography, deposition, inspection, and handling tools.
- Qualification announcements from more than one major packaging provider.
- Published cost-per-good-package data rather than simple area or throughput claims.
- Evidence that multiple leading AI-chip suppliers are shipping products using the format.
What this means for the semiconductor industry
The likely competitive change is not a sudden collapse of wafer fabrication. It is a possible redistribution of value in advanced packaging. Foundries remain essential because the logic and memory dies still originate in wafer-based processes. At the same time, OSATs and specialized packaging providers could capture more high-end heterogeneous-integration work if they can deliver the required yield, density, reliability, and capacity.
The commercial opportunity extends across equipment, substrates, materials, metrology, automation, design services, and contract packaging. But equipment vendors generally sell through negotiated enterprise engagements rather than transparent list pricing, and a tool alone is not a qualified manufacturing process.
The accurate takeaway
AI is not making silicon wafers rectangular. It is making enormous, multi-die packages more difficult and expensive to process efficiently on a circular format. That is why the industry is exploring rectangular panel-level packaging.
Round wafers will remain fundamental to front-end semiconductor manufacturing for the foreseeable future. Panels may become an important format for selected AI and HPC packages if they can overcome warpage, alignment, inspection, yield, equipment, and qualification challenges. The decisive test will be sustained production of good packages at a lower total cost—not the geometry alone.
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