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Modern CPU idle management is no longer a simple choice between “awake” and “asleep.” Linux and contemporary processors predict how long a logical CPU will have no runnable work, select a suitable idle state, apply latency constraints, and coordinate with firmware, sibling cores, devices, and package-level power controllers. The result is a layered system that tries to enter deep idle states when the expected energy savings justify their wake-up cost.
The central trade-off remains unchanged: deeper idle generally offers greater potential power savings, but usually has higher entry and exit latency. The major advances have come from improving prediction, reordering the idle loop, using processor-specific drivers, coordinating hierarchical power domains, and allowing hardware to make more decisions autonomously.
CPU idle time is a control problem, not an off switch
A logical CPU is idle when it has no immediately runnable task. At that point, the operating system can poll for work, execute a shallow halt, or request a progressively deeper low-power state. The correct choice depends on an uncertain question: how long will the CPU remain idle?
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If a timer or interrupt is expected soon, entering a deep state may waste energy because the processor pays an entry and exit cost for only a short sleep. If the idle interval lasts longer than expected, choosing a shallow state leaves potential savings unused. Modern idle management is therefore an optimization under uncertainty, constrained by latency requirements and platform-wide conditions.
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Linux describes this function as CPUIdle. It is separate from CPUFreq, which controls operating performance points while the processor is doing work. A core running at a low frequency is still executing instructions; a core in a C-state is not executing normal instructions. Reducing frequency is not automatically more efficient than finishing work quickly and entering a deep idle state.
C-states, residency, and wake-up cost
C-states describe idle conditions, but their names and physical implementations vary between processor families. A deeper state generally has:
| Characteristic | Shallow idle | Deep idle |
|---|---|---|
| Entry latency | Lower | Higher |
| Exit latency | Lower | Higher |
| Potential power saving | Lower | Greater |
| Useful idle duration | Shorter | Longer |
| Risk of a wasted transition | Lower | Higher |
The relevant metric is not simply the C-state number. It is whether the expected idle interval exceeds the state’s effective break-even point, taking account of entry energy, exit energy, transition latency, and the power saved while resident. A state called C6 on one processor should not be assumed to have the same behavior as C6 on another.
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Idle states can exist at several levels:
- Thread or logical-CPU level: an individual hardware thread has no work.
- Core level: all relevant threads on a core are idle.
- Cluster or shared-domain level: several cores and shared resources can be reduced or powered down.
- Package or system level: the processor package, memory, I/O, or other platform domains meet conditions for deeper savings.
Intel’s low-power idle documentation illustrates why a per-thread request does not necessarily describe the final state of the whole core or package. One active sibling, shared cache, device, or package controller can prevent broader power reduction.
How Linux chooses an idle state
The basic path is:
- The scheduler finds no runnable task for a CPU.
- The idle loop estimates how long the CPU may remain idle.
- The CPUIdle governor compares that estimate with available states, target residencies, exit latencies, and current latency constraints.
- The CPUIdle core invokes a processor- or platform-specific driver.
- Firmware and hardware implement, modify, or reject the requested transition.
- An interrupt, timer, or newly runnable task wakes the CPU.
The governor uses information such as the next timer deadline, recent idle intervals, timer behavior, scheduler activity, and expected wake-ups. It must also respect PM QoS constraints: a state whose resume latency exceeds the current limit cannot be selected.
The kernel’s generic CPUIdle architecture is documented in the CPUIdle core API documentation. Software can count entries and rejected selections, but those counters do not always reveal the exact physical depth reached when one software-visible state represents several hierarchical hardware states.
The prediction problem
Two errors dominate idle-state selection:
- Underprediction: the governor chooses a shallow state even though the CPU remains idle long enough for a deeper state to have paid off.
- Overprediction: the governor chooses a deep state, but an interrupt arrives quickly and the transition cost was unnecessary.
The next timer is useful, but it is not a complete prediction. Network and storage completions, cross-CPU wake-ups, device interrupts, virtualization activity, scheduler events, and background kernel work can all end an idle interval earlier than expected.
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1Scan for outdated or missing drivers - takes under a minute2Repair Windows errors before they cause bigger problems3Fix the driver behind crashes, sound loss and screen glitchesThe scheduler tick adds another complication. A periodic tick can interrupt an otherwise long idle interval. Linux idle-loop work culminating in the Linux 4.17-era redesign changed the ordering of tick handling and idle-state selection to mitigate particular short-idle prediction and tick-interference problems. Rafael Wysocki’s 2018 presentation describes that historical development. It did not eliminate prediction errors: more recent research continues to report missed opportunities to enter deep idle states in latency-sensitive servers, including the effects of inaccurate prediction and long legacy transition costs.
“Tickless” therefore does not mean “interrupt-free.” Network traffic, timers, device polling, accounting, virtualization, and storage activity can still wake a CPU.
Idle governors: menu, ladder, and TEO
Linux has used several CPUIdle governor approaches:
menu: combines timer prediction with workload and idle-history information.ladder: uses a simpler progressively deeper-state selection model and remains available on some configurations.teo: focuses on timer events and recent idle-duration patterns to improve state selection in relevant workloads.
No governor is universally best. Results depend on the kernel version, processor, firmware, interrupt pattern, timer behavior, distribution defaults, and whether the workload is a desktop, laptop, server, or real-time system. A newer governor is not automatically more efficient.
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cpuidle.governor=menuVerify the available choices rather than assuming a governor exists:
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cat /sys/devices/system/cpu/cpuidle/current_governor
cat /sys/devices/system/cpu/cpuidle/available_governorsProcessor-specific intelligence: Intel idle management
Generic CPUIdle infrastructure needs a driver that maps abstract states to the processor’s mechanisms. On Intel systems, intel_idle can use static tables for recognized processor models, processor capabilities discovered through CPUID, MWAIT information, and firmware-provided ACPI data.
This makes the available state list platform-specific. A processor model may support a state in principle while firmware, kernel recognition, or platform policy prevents it from being exposed.
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Repair Windows errors before they cause bigger problemsFix Now →Scan for outdated or missing drivers - takes under a minuteDriver Scan →Intel systems also demonstrate why an operating-system request is not necessarily the final physical result. Linux may request a deep state such as C6, while firmware monitors wake-up frequency and demotes frequent short sleeps to a shallower state such as C1. After a sufficiently long idle interval, the platform may promote the request again. The intel_idle documentation calls this behavior C1 demotion.
Consequently, “Linux selected C6” should be read as “Linux selected or requested a software-visible state associated with that idle path,” not as proof that every part of the processor entered a particular physical power condition.
Idle states and active performance states are different
CPUIdle answers whether and how deeply the CPU sleeps when it has no work. CPUFreq answers which frequency and voltage or operating performance point to use while it works. They interact, but neither replaces the other.
Modern performance control is also increasingly autonomous. AMD’s amd-pstate driver uses the Collaborative Processor Performance Control interface on supported processors. It supports active/autonomous, passive/non-autonomous, and guided autonomous modes, along with energy-performance preferences and preferred-core information.
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The same distinction applies to CPUFreq generally. A frequency reading is not a direct measurement of package power, and low frequency does not guarantee low energy if the processor remains active, the fabric and memory are busy, or the package cannot reach a deep idle state.
From per-core sleep to hierarchical power management
Modern processors contain multiple interacting power domains: logical threads, cores, clusters, shared caches, fabrics, memory controllers, I/O, and the package itself. Deeper package states may require all relevant cores and devices to be sufficiently idle.
This creates effects that a simple per-CPU idle percentage cannot explain:
- One active sibling can prevent a core-level state.
- One busy core can keep shared cache or fabric resources powered.
- A network or storage device can generate frequent wake-ups.
- A latency-sensitive device can impose a platform constraint.
- Firmware can demote a request after observing frequent exits.
- Virtual-machine scheduling can change the apparent idle intervals.
The correct mental model is hierarchical residency, not a single global “CPU asleep” indicator. Package C-state residency, core residency, interrupt rates, and device activity may matter more than average idle time.
ARM and non-x86 approaches
ARM systems do not form one uniform model, and x86 C-state terminology should not be mapped onto them mechanically. Depending on the platform, Linux may use architectural idle instructions, PSCI firmware interfaces, ACPI or device-tree descriptions, and platform-specific power-domain controllers.
Mobile and embedded systems often expose explicit per-core, cluster, retention, and system-suspend states. ARM servers may use different firmware and power-domain arrangements. The common principle is the same: a software request describes intent, while firmware and hardware decide what can be implemented given shared resources, wake-up requirements, and platform policy.
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Measure the platform instead of guessing
Inspect available idle states
Typical Linux systems expose CPUIdle data below:
/sys/devices/system/cpu/cpu*/cpuidle/State directories commonly contain files such as name, latency, residency, usage, rejected, and disable. The exact set varies.
for f in /sys/devices/system/cpu/cpu0/cpuidle/state*/*; do
printf '%s: ' "$f"
cat "$f"
doneFor all CPUs:
find /sys/devices/system/cpu -path '*/cpuidle/state*/*' -type f -printDo not assume that state2 means C2 on every machine. Sysfs indices are driver-specific.
Check the scaling driver separately
cpupower frequency-infoThis helps distinguish the CPUIdle driver and governor from the CPUFreq driver, scaling policies, and performance-state information. It does not turn a reported frequency into a package-power measurement.
Measure residency, wake-ups, and energy
For a meaningful investigation, collect idle-state residency, usage and rejection counters, package and core residency, interrupt rates, timer activity, CPU migrations, device wake-ups, and wall or package energy. Common tools include:
turbostat
powertop
perf stat
cpupower monitorTool output, counter names, privileges, and accuracy vary by distribution and hardware. Where possible, validate conclusions with wall power or platform energy counters rather than inferring energy from frequency alone.
Latency constraints and diagnostic controls
Linux PM QoS can limit the maximum acceptable CPU resume latency. The documented interfaces include /dev/cpu_dma_latency and per-CPU controls such as:
/sys/devices/system/cpu/cpu<N>/power/pm_qos_resume_latency_usA latency constraint should be held only for as long as the latency-sensitive operation requires. A process using /dev/cpu_dma_latency must keep the file descriptor open; closing it releases that constraint. Exact setup should be integrated with the application or service rather than copied casually into a shell experiment.
An individual state can sometimes be disabled temporarily:
echo 1 | sudo tee /sys/devices/system/cpu/cpu0/cpuidle/state<N>/disable
echo 0 | sudo tee /sys/devices/system/cpu/cpu0/cpuidle/state<N>/disableThis is per CPU and may be restricted by the driver. Treat it as an experiment with before-and-after measurements, not a permanent optimization.
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Useful boot parameters include:
cpuidle.off=1
cpuidle.governor=menu
idle=poll
idle=halt
idle=nomwait
intel_idle.max_cstate=<n>
processor.max_cstate=<n>These have important consequences. cpuidle.off=1 disables normal CPUIdle drivers and governors. idle=poll keeps idle CPUs polling and can substantially increase power use. It can also interfere with package-level performance behavior and sometimes reduce performance. idle=halt targets the architecture’s halt mechanism. idle=nomwait prevents MWAIT use and, on Intel, disables intel_idle in favor of acpi_idle when adequate ACPI information exists. The maximum-C-state parameters hide deeper states from the relevant driver; intel_idle.max_cstate=0 disables the Intel driver, while processor.max_cstate=0 has different semantics.
These options are primarily compatibility and diagnostic controls. Disabling deep states to solve a latency problem can increase power, temperature, fan activity, and battery drain without addressing the actual source of wake-ups.
Troubleshooting by symptom
High idle percentage but high power consumption
Average idle time may be fragmented into many short intervals. Check idle-duration distribution, deep-state residency, wake-up frequency, interrupt sources, device runtime power management, and package residency. A CPU can be “idle” often without ever remaining idle long enough for deep savings.
The system requests a deep state but monitoring shows a shallow state
This can be normal. Firmware may demote frequent deep-state requests, and hardware may choose a different physical condition from the software-visible state. Compare request, residency, rejection, wake-up, and package-level data before treating the result as a kernel fault.
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Disabling deep C-states improves latency but worsens everything else
The expected costs include higher idle power, more heat, reduced battery life, less package-level savings, and potentially less turbo headroom. If latency improves, identify whether the gain came from reduced transition latency or from suppressing a source of wake-up variability. The remedy may instead be interrupt affinity, device configuration, scheduler isolation, or a narrowly scoped PM QoS constraint.
idle=poll makes performance worse
This is explicitly possible. Polling prevents normal idle power savings and can block package conditions that help active performance states. Keep it for controlled diagnostics or narrow debugging cases, not as a generic performance setting.
A newer processor idles worse than an older one
Possible explanations include different firmware defaults, more shared domains, higher platform baseline power, incomplete driver recognition, more active devices, more frequent interrupts, or higher deep-state transition costs. Compare the complete platform rather than the processor model alone.
A virtual machine behaves differently
A guest sees virtual CPUs, not necessarily physical cores. Hypervisor scheduling, vCPU overcommit, virtual timers, paravirtualized idle mechanisms, and host power policy can dominate the result. Guest C-state observations should not be treated as bare-metal measurements.
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Choosing a policy objective
Battery life
Favor deep package residency, low interrupt and timer activity, working device runtime power management, firmware support for low-power states, and an appropriate balanced or energy-saving policy. Do not disable C-states merely because a system feels briefly less responsive; diagnose the wake-up path first.
Latency
Define the maximum acceptable and tail wake-up latency, not just average latency. Use interrupt locality, CPU affinity, isolation where appropriate, and PM QoS constraints. Shallow states may be appropriate for a latency-critical CPU, while other CPUs can continue using deeper states.
Throughput
Consider whether unused cores entering deep idle gives active cores more thermal or power headroom. Idle states and performance states can reinforce each other; disabling idle behavior can sometimes reduce rather than increase burst performance.
Datacenter efficiency
Measure energy per completed request, throughput per watt, tail latency, rack power, package residency, wake-up rates, and the effect of interrupt moderation and polling. Bursty services may have valuable idle windows between requests, but only if the platform can exploit them.
What comes next
Current research continues to focus on missed deep-idle opportunities and transition overhead. Proposed directions include faster transitions, finer-grained power gating, context retention, hardware-assisted prediction, better scheduler-governor cooperation, and workload-aware placement. The AgileWatts proposal, for example, explores reducing deep-idle transition costs for latency-sensitive servers through finer-grained power gating and context retention. It is a research proposal, not a generally available production feature.
The likely direction is not a single universally superior governor. It is closer coordination between scheduler behavior, idle prediction, processor hardware, firmware, device power management, and package-level controllers. Hardware autonomy can improve responsiveness to conditions the operating system cannot predict, but it does not eliminate operating-system policy: Linux still determines scheduling, constraints, preferences, and workload placement.
Conclusion
The best idle policy matches the workload’s actual idle-interval distribution and latency target. Evaluate it on the real platform using state residency, wake-up sources, package energy, and application latency—not CPU idle percentage or a single frequency reading.
The practical hierarchy is straightforward: separate C-states from P-states; understand the governor’s prediction problem; verify the processor-specific driver and firmware; account for siblings, devices, and package domains; and change one constraint at a time. Deep idle is valuable when the interval is long enough, but measurement—not the state name or a generic boot parameter—determines whether it is helping.
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