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AMD’s November 8, 2021 preview introduced two Zen 4-generation EPYC families with different priorities: Genoa for broad, general-purpose server performance with up to 96 standard Zen 4 cores, and Bergamo for cloud-native density with up to 128 power-optimized Zen 4c cores. They were previews rather than shipping launches. Genoa became the EPYC 9004 family in November 2022; Bergamo followed as EPYC 97×4 in June 2023.
What AMD announced on November 8, 2021
AMD disclosed the Genoa and Bergamo codenames, along with its Zen 4 and Zen 4c server-core strategy. Genoa was planned for 2022 and targeted general-purpose data-center computing. Bergamo was planned for the first half of 2023 and targeted cloud-native, scale-out deployments. AMD identified Cisco, Dell Technologies, Lenovo, HPE and Supermicro among its server partners. The announcement covered future products, not processors available for immediate purchase. AMD’s announcement also highlighted DDR5, PCIe 5.0, CXL and the SP5 platform.
| Family | 2021 status | Commercial identity | Representative launch |
|---|---|---|---|
| Genoa | Preview; planned for 2022 | EPYC 9004, including EPYC 9654 | EPYC 9654 launched November 10, 2022 |
| Bergamo | Preview; planned for first half of 2023 | EPYC 97×4, including EPYC 9754 | EPYC 9754 launched June 13, 2023 |
Genoa: the general-purpose Zen 4 design
Genoa uses conventional Zen 4 cores and was intended to balance per-core responsiveness, cache capacity, memory bandwidth and broad software compatibility. Typical targets include enterprise applications, relational databases, virtualization, web services, technical computing and general-purpose cloud instances. It is the safer choice when a server must run a mixed portfolio rather than a consistently parallel fleet.
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- 96 cores and 192 threads
- 2.4 GHz base clock and up to 3.7 GHz boost
- 384 MB L3 cache
- 360 W default TDP; configurable from 320 W to 400 W
- 12-channel DDR5 memory, up to DDR5-4800
- Up to 128 PCIe 5.0 lanes
- SP5 socket with one- or two-socket support
- AMD-listed 1,000-unit price signal of $8,452 on the retrieved product page; this is not a current retail or complete-system price
Specifications and pricing are from AMD’s EPYC 9654 page. The single-socket EPYC 9654P retains 96 cores, 192 threads, 384 MB of L3 and a 360 W rating, but supports only one-socket systems; AMD listed a 1,000-unit price signal of $7,272 on its product page (EPYC 9654P specifications).
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Bergamo: density-first Zen 4c
Bergamo replaces standard Zen 4 with Zen 4c, a density- and power-efficiency-oriented implementation. AMD designed it to fit more cores into a similar server-platform envelope while retaining the same software and security model. Zen 4c is not an incompatible “small core” instruction-set class, and it is not simply Genoa with 32 extra cores. Its lower-frequency, denser design favors aggregate throughput over maximum per-thread speed.
EPYC 9754 example
- 128 cores and 256 threads
- 2.25 GHz base clock and up to 3.1 GHz boost
- 256 MB L3 cache
- 360 W default TDP; configurable from 320 W to 400 W
- 12-channel DDR5 memory up to 4800 MT/s
- Up to 128 PCIe 5.0 lanes
- SP5 socket with one- or two-socket support
- AMD-listed 1,000-unit price signal of $10,631 on the retrieved product page
See AMD’s EPYC 9754 specifications. AMD also introduced the 112-core EPYC 9734. Launch-period coverage reported 2.2 GHz base, up to 3.0 GHz boost, 320 W TDP and 256 MB L3; those figures should be treated as launch specifications rather than a universal Bergamo specification (Tom’s Hardware coverage).
Rank #2
- Sockel SP5, 64 x 3.1 GHz (Boost 3.75) GHz
- 384 MB L3 Cache, 64 cores/ 128 threats
- 12-channel memory support up to DDR5-4800 MHz
- Max. Performance consumption 360 watts (structural width 5 Nm)
- Tray (without cooler)
Genoa versus Bergamo at a glance
| Characteristic | EPYC 9654 (Genoa) | EPYC 9754 (Bergamo) |
|---|---|---|
| Core design | Zen 4 | Zen 4c density-optimized derivative |
| Cores / threads | 96 / 192 | 128 / 256 |
| Base / boost | 2.4 / up to 3.7 GHz | 2.25 / up to 3.1 GHz |
| L3 cache | 384 MB | 256 MB |
| Default TDP | 360 W | 360 W |
| Memory and I/O | 12-channel DDR5 up to 4800; 128 PCIe 5.0 lanes | 12-channel DDR5 up to 4800; 128 PCIe 5.0 lanes |
| Socket | SP5; 1P/2P | SP5; 1P/2P |
| Primary design goal | Balanced, general-purpose performance | Cloud-native density and throughput |
| AMD 1,000-unit price signal | $8,452 | $10,631 |
Why AMD pursued two families
Cloud platforms often run thousands of containers, microservices, front-end services or relatively lightweight virtual machines. Those applications can keep many threads busy and reward more cores per socket, more work per rack unit and better throughput per watt. Bergamo’s 128 cores therefore address a different optimization target from Genoa’s higher clocks and larger L3 cache.
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1Scan for outdated or missing drivers - takes under a minute2Clear out junk files and repair common Windows errors3Fix the driver behind crashes, sound loss and screen glitchesGenoa is generally the stronger starting point for relational databases, unevenly scaled enterprise software, mixed virtualization, latency-sensitive services and applications that benefit from larger per-core resources. Bergamo is better suited to container fleets, high-density VMs, scale-out Java services, parallel data services and other workloads designed to distribute work across many threads.
Rank #3
AMD reported approximately 2.84× performance for a two-socket EPYC 9754 system across selected cloud-native tests against specified competing systems. That is an AMD-supplied, workload- and configuration-specific result, not a universal multiplier (AMD cloud-native brief).
More cores do not guarantee more useful performance
A 128-core processor can lose to a 96-core processor when software has a serial bottleneck, depends heavily on frequency, cannot keep all threads busy or suffers from synchronization and memory contention. NUMA placement, storage and network limits can also dominate. Per-core software licensing may make a denser CPU more expensive to operate even when its throughput is higher.
Rank #4
- Compare performance per core, total socket throughput, performance per watt, rack density and performance per dollar separately.
- Measure latency under realistic load; aggregate throughput can improve while tail latency worsens.
- Check whether the application scales past dozens of cores before paying for 96 or 128.
- Do not treat TDP as a guaranteed measure of wall power.
The common SP5 platform
Genoa and Bergamo share AMD’s SP5 ecosystem: 12 DDR5 memory channels, support up to DDR5-4800, up to 128 PCIe 5.0 lanes, one- or two-socket configurations depending on SKU, Infinity Architecture and Infinity Guard security features. AMD specifically highlighted CXL support for Genoa for memory expansion and related data-center uses (AMD architecture overview).
Socket compatibility does not mean a processor will work in every SP5 server. Confirm OEM BIOS and firmware support, board validation, power delivery, cooling capacity and the supported CPU stepping. Populate memory channels symmetrically, validate NUMA and process placement, and decide whether SMT should remain enabled for your workload.
Best Value
- Socket SP3 Enables PCB Placement Without Soldering
- Processor Equipped with Socket SP3 for PCB Installation
- EPYC Processor Ensures Reliability and Maximum Productivity
- 128 MB L3 Cache Boosts System Performance, Minimizes Interruptions
- 24-Core Processor Core Handles Data Efficiently for Quick Information Transfer
Deployment checks and failure modes
- Firmware: A matching socket is insufficient if BIOS, AGESA or microcode lacks the required SKU or stepping.
- Thermals: A 320–400 W configurable envelope requires a qualified chassis, heatsink and rack-power budget.
- Memory: Unbalanced DIMM population can reduce bandwidth and erase the benefit of a high-core-count CPU.
- NUMA: Cross-socket traffic and poor thread placement can add avoidable latency.
- SMT: The 9754 exposes 256 threads, but operators may disable SMT for determinism, licensing or security policy.
- Maintenance: Keep server firmware and microcode current; AMD’s security bulletin lists Genoa and Bergamo mitigation guidance (AMD security bulletin).
What actually shipped and what it means now
The preview became the 4th Gen EPYC 9004 family for Genoa and EPYC 97×4 for Bergamo. The EPYC 9654 represents the 96-core general-purpose design; the EPYC 9754 represents the 128-core density design. Product availability and pricing vary by region, OEM, contract volume and whether the CPU is bought as a tray component or inside a supported server.
As of August 18, 2026, these are not AMD’s newest EPYC products: AMD launched 5th Gen EPYC in October 2024 (AMD launch announcement). The 2021 preview remains significant because it established AMD’s two-track server strategy: standard high-performance cores for diverse enterprise computing and density-optimized cores for cloud-scale parallel work.
Choosing between them
Choose Genoa when
- Single-thread responsiveness or uneven scaling matters.
- Databases, enterprise applications or mixed VM workloads dominate.
- Larger L3 cache and higher clocks are valuable.
- Per-core licensing or certification discourages extreme density.
Choose Bergamo when
- Containers, microservices or VMs can use hundreds of threads.
- Throughput per socket, rack unit or watt is the main objective.
- The software scheduler and application architecture scale cleanly.
- You want more capacity without moving to a larger server footprint.
For a 2026 procurement, compare these older 4th Gen parts with current 5th Gen EPYC systems and calculate total cost of ownership, including memory, licensing, power, support and the server chassis—not just the processor’s historical list-price signal.
Quick Recap
Product prices and availability are accurate as of the date/time indicated and are subject to change. Any price and availability information displayed on Amazon at the time of purchase will apply.
