Some links on this page are affiliate links: if you buy through them we may earn a commission, at no extra cost to you.
TV80 is a Verilog RTL processor core intended to execute the 8080 and Z80 instruction sets. It is reusable hardware-design source for an FPGA or ASIC—not a finished Z80 chip, emulator, development board, or complete computer. OpenCores describes it as mature, FPGA- and ASIC-proven, and BSD-licensed, but its public release artifacts are old enough that every new adopter should pin a source revision and verify compatibility, timing, and tool support.
What TV80 is
TV80 is an 8-bit microprocessor IP core hosted in the OpenCores ecosystem. The Verilog implementation derives from Daniel Wallner’s VHDL T80 core and is designed to execute the 8080/Z80 instruction set. OpenCores also describes its cycle timing as similar to the original Z80 and lists FPGA and ASIC use. See the OpenCores TV80 overview and the All About Circuits listing.
In practical terms, an IP core is RTL that you incorporate into a larger hardware design. You obtain the source, instantiate the processor, provide clock and reset, connect memory and I/O, add interrupt and bus-control logic, simulate it, and then synthesize it for your target device or process.
The Tool Desk
Outbyte Driver Updater FREEFix the driver behind crashes, sound loss and screen glitchesFind Drivers →Outbyte PC Repair FREERepair Windows errors before they cause bigger problemsFix Now →TV80 does not include a complete address space, RAM, ROM, operating system, video circuit, UART, board support package, FPGA image, or packaged semiconductor. A physical Z80 cannot simply be replaced pin-for-pin by importing this RTL into an FPGA; external I/O adaptation and system-level verification are required.
#1 Best Overall
- Duplicate set of both general-purpose and fiag registers.
- Two sixteen-bit index registers
- 6 MHz version can be operated at 6.144 MHz clock
- On-chip dynamic memory refresh counter
- NOTE:Exposure to absolute maximum rating conditions for extended periods may affect device reliability. We do not provide technical support, please familiarize yourself with the parameters and performance of the purchased products in advance. Sincerely apologize for you.
The project was created on May 14, 2004. OpenCores shows an overview update on January 30, 2019 and an SVN update on February 2, 2012. Those dates indicate a long-lived project, not an active 2026 support commitment.
Advertised specifications and implementation history
| Item | What is documented | How to interpret it |
|---|---|---|
| Core type | 8-bit Z80-compatible microprocessor core | Compatibility claims require testing for the behavior your system depends on. |
| HDL | Verilog | Suitable for Verilog/SystemVerilog-centered FPGA or ASIC flows, subject to tool compatibility. |
| Instruction support | 8080/Z80 instruction set | Does not by itself prove identical undocumented opcodes, flags, interrupts, or bus behavior. |
| Timing | Timing similar to the original Z80 | This is the project’s wording, not a formal cycle-equivalence certification. |
| License | BSD, according to OpenCores | Check the exact license text in the source package and preserve required notices. |
| Wishbone | Base project marked not Wishbone-compliant; optional wrapper available | The wrapper must be evaluated separately for latency, waits, and interrupt mapping. |
| Historical ASIC result | Approximately 20,000 gates at approximately 250 MHz in TSMC 130 nm | Historical project data, not a portable area or frequency guarantee. |
| Historical ASIC result | TSMC 65 nm at 125 MHz | The overview does not provide enough PVT, library, constraint, or design-scope detail to generalize this figure. |
| Project status | Mature; FPGA- and ASIC-proven in OpenCores metadata | A status label is not a current support contract or verification certificate. |
OpenCores also lists a sample peripheral with a GMII interface and an optional Wishbone wrapper. These are surrounding components or integration options, not evidence that the base processor is natively Wishbone-compliant. The authoritative project description is at opencores.org/projects/tv80.
What “Z80-compatible” does—and does not—establish
Compatibility has several layers. TV80’s public description directly supports an 8080/Z80 instruction-set goal and similar cycle timing, but it does not publish a complete conformance matrix proving every behavior of every physical Z80 revision.
What’s actually slowing this PC down?
Pick the symptom - the matching free tool is one click away.
Instruction compatibility
Documented 8080 and Z80 instructions are the central target. Test prefixed instructions, block operations, flag results, memory instructions, and I/O instructions rather than assuming that a broad label covers every corner case.
Rank #2
- PMMCON Pack of 2, Z80 CPU Microprocessor IC DIP-40 Z84C0020PEC Z80CPU Z80-CPU
- The Z84C0020PEC is Z80 Microprocessor IC Z80 1 Core, 8-Bit 20MHz 40-PDIP.
- Package/housing 40-DIP (0.620 ", 15.75mm)
- I/O-40°C ~ 100°C（TA）
- Description: IC MPU Z80 20MHZ 40DIP
Cycle and bus compatibility
A processor may execute the same instructions while presenting different machine-cycle details. Validate address and data-bus direction, read and write strobes, wait-state insertion, refresh signaling, interrupt acknowledge cycles, HALT, BUSRQ, and BUSACK against the device or vintage system you intend to reproduce.
Undocumented behavior
Programs or peripherals that rely on unofficial opcodes, undocumented flag behavior, refresh-register details, interrupt-mode subtleties, or vendor-specific bus quirks need targeted comparison with a trusted Z80 reference. “Z80-compatible” should not be expanded into “every undocumented behavior is identical.”
Electrical and pin compatibility
RTL compatibility is not electrical equivalence. An FPGA implementation still needs I/O standards, voltage decisions, clocking, reset synchronization, tri-state or muxing strategy, and board-level adaptation. An ASIC requires pads, power domains, physical design, timing signoff, and package decisions.
Do these 3 things before closing this tab:
1Fix the driver behind crashes, sound loss and screen glitches2Repair Windows errors before they cause bigger problems3Scan for outdated or missing drivers - takes under a minuteWhere to obtain the source
The OpenCores downloads page lists tv80_rel1.0.zip, dated July 12, 2005, plus an earlier complete CVS snapshot dated May 17, 2004. The repository tree and its revision log expose later history and test-related changes.
Rank #3
- 【Outstanding Performance】We use high-quality materials to ensure a for perfect fit between all components and equipment.
- 【Product Quality】Installation is simple, time and effort.
- 【Professional Factory】We have a professional factory, and all products comply with for safety standards.
- 【Excellent Service】We have a professional team to provide support for you，If you have any questions, please for contact us promptly.
- 【Reservation Confirmation】Please verify the product model and applicable year to ensure it meets your needs.
The archive is easier to reproduce historically; a repository revision may contain later fixes or test infrastructure. Preserve a local copy, record the exact revision or archive checksum, and do not build a production flow around an unpinned “latest” download. Downstream copies can be useful, but provenance and modifications must be checked. For example, rejunity/z80-open-silicon identifies use of Guy Hutchison’s TV80 Verilog core; that demonstrates reuse, not canonical-maintainer status.
Integrating TV80 into an FPGA or ASIC
- Select and pin a source. Choose the release archive for historical reproducibility or inspect repository revisions for later fixes. Keep the license and source files together.
- Identify the actual top level. Determine whether you are instantiating the native TV80 core, a simple wrapper, or an optional Wishbone interface. Do not assume their ports or timing are interchangeable.
- Compile before synthesis. Run the supplied testbench and scripts where practical, then compile with the simulator used by your own CI. The revision history records Verilator-related fixes and the project log records Icarus Verilog work, so modern-tool compatibility should be demonstrated rather than presumed.
- Provide the system around the CPU. Add ROM/RAM, address decoding, I/O decoding, interrupt generation, wait-state logic, clock and reset control, and any UART, timer, video, DMA, or bus-arbitration hardware your design needs.
- Audit signal polarity and sequencing. Check active-low reset, WAIT, interrupt, NMI, BUSRQ, memory request, I/O request, read, and write signals. The repository history includes an inverted
wait_nfix, making directed wait-state tests particularly important. - Verify behavior. Compare instructions, flags, cycle counts, interrupts, refresh, HALT, wait states, and bus relinquishment with a trusted reference before relying on the core.
- Synthesize for the real target. FPGA LUTs, block RAM use, fMAX, and ASIC area depend on the wrapper, constraints, memory implementation, target family or cell library, synthesis version, and PVT assumptions. Historical OpenCores numbers cannot substitute for your own reports.
- Integrate and sign off. For ASIC use, complete normal CDC, reset, DFT, physical-design, timing, power, and reliability signoff. For FPGA use, verify the generated bitstream on the actual board and its peripherals.
Verification checklist
- Execute every documented instruction group, including IX/IY prefixes and block instructions.
- Check arithmetic, undocumented or edge-case flags, register exchanges, stack operations, and reset state.
- Exercise maskable interrupts, NMI, interrupt enable/disable timing, interrupt modes, and acknowledge cycles.
- Insert zero, one, and multiple wait states on memory and I/O accesses; include interrupt acknowledge and HALT cases.
- Check WAIT, BUSRQ, BUSACK, refresh, and bus release timing at the external interface.
- Confirm active-low conventions and reset behavior in the selected top-level module.
- Run the same tests in the intended simulator and FPGA vendor synthesis tool; review warnings about legacy Verilog constructs, sensitivity lists, signedness, and inferred storage.
- Compare cycle traces and flags against a known-good Z80 model when software or hardware depends on exact behavior.
License and project-risk considerations
OpenCores lists TV80 under a BSD license. BSD-style terms are generally permissive: they commonly allow use, modification, and redistribution, including in commercial hardware, while requiring preservation of copyright and license notices. The exact text in the package you use controls; inspect it file by file and review any bundled third-party components.
A permissive license does not provide a warranty, compatibility guarantee, technical support obligation, patent clearance for an entire product, or protection from system-level liability. The adopter remains responsible for verification, documentation, export and compliance review, and product signoff.
When TV80 is a good fit
- You need source-level control of an 8080/Z80-like CPU in a Verilog FPGA or ASIC design.
- Legacy software compatibility matters more than adopting a new instruction-set ecosystem.
- You can perform your own simulation, integration, and compatibility testing.
- A permissive open-source license and a compact historical implementation are useful.
- You are building a retro system, homebrew console, research design, or custom SoC.
When another option is safer
- Your product requires contractual vendor support, formal warranties, or current verification collateral.
- Pin-level and undocumented-behavior equivalence to a particular physical Z80 is mandatory.
- Your team cannot budget time for legacy RTL cleanup, simulator porting, or wrapper validation.
- You require a modern standard-bus interface without maintaining and testing an adapter.
- You are starting a new software ecosystem with no Z80/8080 compatibility requirement; a maintained RISC-V soft core may be a better architectural fit.
Alternatives to compare
Daniel Wallner’s T80
T80 is the VHDL predecessor identified by the TV80 project. It can be preferable for VHDL-first designs or teams with existing T80 verification infrastructure; TV80 is more natural for Verilog-oriented flows.
Other OpenCores Z80 cores
The OpenCores processor index lists alternatives including wb_z80, described as derived from TV80, and y80e, described as a Z80/Z180-compatible Verilog core. Compare HDL, bus protocol, compatibility scope, verification, update history, license, examples, and resource use rather than choosing by name alone.
Physical Z80-compatible hardware
A physical processor is more appropriate when an existing board demands vintage voltage, bus, clock, and pin behavior without adding an FPGA. TV80 is more appropriate when the CPU must live inside an FPGA or custom SoC or be modified at RTL.
Modern RISC-V
RISC-V generally offers a better foundation for a new toolchain and software ecosystem. It is not an instruction-compatible replacement for Z80 software, so it does not solve a legacy-compatibility requirement.
Bottom line for 2026 adopters
TV80 remains a credible starting point for an open FPGA or ASIC design that needs a Z80/8080-style processor and accepts responsibility for verification. Its strengths are visible RTL, permissive BSD licensing, historical implementation evidence, and a long record in the OpenCores ecosystem. Its limits are equally important: old release artifacts, maintenance-light public history, no complete computer system, no proof of pin-level or undocumented-behavior equivalence, and no current vendor support promise.
Use a pinned source snapshot, test the exact interfaces and behaviors your design needs, and treat the OpenCores frequency and gate figures as historical context—not as specifications for your device.
Quick Recap
Product prices and availability are accurate as of the date/time indicated and are subject to change. Any price and availability information displayed on Amazon at the time of purchase will apply.
