MOSFETs Explained: How Insulated-Gate Field-Effect Transistors Work

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A MOSFET is an insulated-gate field-effect transistor: a voltage on its gate controls current between its drain and source through an electric field. The gate draws very little steady-state current, but it must be charged and discharged to switch, and choosing a usable device requires more than checking its threshold voltage or headline current rating.

IGFET is the broader category; MOSFET is its most widely used member. This guide connects the device’s structure and operating modes to datasheet reading, switching circuits, and practical selection.

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What does MOSFET mean?

MOSFET stands for metal–oxide–semiconductor field-effect transistor. A field-effect transistor (FET) controls current in a semiconductor channel using an electric field. In an insulated-gate FET (IGFET), a dielectric separates the gate from the semiconductor, so the gate does not directly inject control current into the channel.

The gate, dielectric, and semiconductor act like a capacitor. That means a MOSFET needs negligible steady-state gate current in the idealized sense, but real gates have leakage and require current while their capacitance is charged or discharged. The practical distinction is important: a MOSFET is voltage-controlled, but a driver may still need to deliver substantial short-duration current to switch it quickly.

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IGFET is an umbrella term, while MOSFET describes a metal–insulator–semiconductor gate structure. “Metal” and “oxide” are historical terms: modern devices may use polysilicon or metal gates and complex dielectric stacks. MISFET is another broad term for a metal–insulator–semiconductor FET. In everyday circuit work, MOSFET and IGFET are often used almost interchangeably, but MOSFET is the specific and familiar term.

Field-effect transistors
├── Junction-gate FETs, including JFETs
└── Insulated-gate FETs, including MOSFETs and related structures

MOSFETs appear in digital logic and processors, analog amplifiers, RF circuits, motor drives, battery systems, and power converters. Manufacturer portfolios include small-signal and power devices, silicon and silicon-carbide (SiC) parts, and devices spanning a wide range of voltage classes. See the ST power MOSFET portfolio and Toshiba’s silicon and SiC MOSFET information.

Terminals and construction

A MOSFET is commonly described as a four-terminal device:

• Gate (G): the control terminal, insulated from the channel by a dielectric.
• Drain (D) and source (S): the two terminals for channel current. Their roles and current direction depend on the device and circuit.
• Body, bulk, or substrate (B): the semiconductor material in which the channel forms. In many discrete power MOSFETs the body is internally connected to the source.

A conventional N-channel device has a P-type body with N-type source and drain regions. With the gate at the right voltage relative to the source, electrons gather near the semiconductor surface under the gate and form a channel between source and drain. A P-channel device uses opposite carrier types and polarities.

In many discrete power MOSFETs, the source-connected body creates an intrinsic body diode between drain and source. Its direction and characteristics matter in real circuits; it is not an optional external component or an ideal diode. Consult the particular device’s datasheet, especially for reverse-recovery behavior in bridge and synchronous-converter circuits. ST’s MOSFET overview discusses body diodes and device capacitances.

How gate voltage turns a MOSFET on

Consider an N-channel enhancement-mode MOSFET, the common choice for switching:

1. At approximately zero gate-to-source voltage, V_GS, it is normally off apart from leakage.
2. As V_GS becomes positive, the gate’s electric field attracts electrons toward the semiconductor surface.
3. At a threshold condition, an inversion channel begins to form.
4. Increasing gate voltage strengthens the channel and reduces its resistance.
5. The device is adequately enhanced for a switching design only when the applied gate voltage yields a suitable specified on-resistance.

Threshold voltage, V_GS(th), is not the voltage required for full turn-on. It is measured at a low drain current and indicates the onset of conduction under stated test conditions. It does not tell you that the transistor can carry its intended load current efficiently. Check the datasheet’s guaranteed R_DS(on) at the gate voltage your circuit can actually provide.

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For example, a datasheet may specify on-resistance at 10 V and separately at 4.5 V. That gives evidence about those drive conditions. A threshold figure alone cannot establish that a device will work well from a 3.3 V microcontroller. The NXP MOSFET application handbook explains the dependence of on-resistance on gate voltage and temperature; see also this Infineon datasheet example.

Enhancement and depletion modes

Enhancement-mode MOSFETs are normally off at zero gate-to-source voltage and need the correct gate polarity to form a channel. They dominate digital logic and ordinary power switching.

Depletion-mode MOSFETs are normally on at zero gate-to-source voltage. Applying a gate voltage of the appropriate reverse polarity depletes the channel and reduces current. Depletion devices are used in specialized circuits such as current sources, startup circuits, and some protection or high-voltage applications. In an ordinary circuit discussion, “MOSFET” usually means an enhancement-mode part, but the distinction should not be assumed where a design depends on the default state.

N-channel and P-channel devices

N-channel MOSFETs use electrons as the majority carriers; P-channel devices use holes. Electron mobility is higher, so for comparable silicon technology and die area, an N-channel device can generally achieve lower on-resistance. N-channel parts are therefore common in efficient power switching, low-side switches, and synchronous rectifiers.

A P-channel MOSFET can simplify a high-side switch: with its source tied to the positive rail, pulling the gate lower than the source turns it on. The trade-off is generally higher on-resistance than a comparable N-channel device, which can mean greater conduction loss at high current. An N-channel high-side switch often needs a gate voltage above its source, supplied by a bootstrap circuit, charge pump, isolated driver, or suitable integrated driver.

Polarity and logic-level capability are separate properties. An N-channel device is not necessarily fully enhanced by a 3.3 V GPIO, and a P-channel device is not automatically the best or safest high-side choice. Check the specified on-resistance and gate limits for the actual circuit.

Operating regions—and a terminology trap

• Cutoff: the channel is not sufficiently formed and current is mainly leakage.
• Linear or triode region: the channel conducts along its length; with adequate gate drive, a switching MOSFET behaves approximately as a low resistance in this region.
• Saturation or active region: the channel pinches near the drain and current is more strongly controlled by gate voltage than by drain voltage. This is useful for analog amplification and current-source behavior.

Power-electronics shorthand can be confusing: engineers sometimes say a switch is “saturated” to mean it is fully on. In textbook MOSFET terminology, saturation is a distinct active operating region and is not the low-resistance switch state. When a design or datasheet uses the word, check what meaning is intended.

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Conduction, switching, and gate charge

When fully enhanced, a MOSFET’s first-order conduction loss is:

Pcond = ID2 × RDS(on)

Current is squared: doubling current produces about four times the conduction loss if resistance stays constant. In practice, on-resistance rises as the junction heats, so use a hot resistance estimate rather than relying only on a room-temperature typical value. The gate voltage, drain current, temperature, and other test conditions attached to the datasheet’s resistance figure matter. See Analog Devices’ note on MOSFET selection and thermal considerations.

A MOSFET’s gate is capacitive. Important switching quantities include total gate charge Q_G, gate-source charge Q_GS, and gate-drain or Miller charge Q_GD. Datasheets also list capacitances such as input C_iss, output C_oss, and reverse-transfer C_rss; these vary with voltage, so a single capacitance value does not tell the whole switching story.

Useful first-order estimates are:

IG,avg ≈ QG × fSW
Pgate ≈ QG × VGS × fSW

They estimate average driver demand and gate-drive power, not total MOSFET loss. Switching loss also depends on drain voltage and current, rise and fall times, driver impedance, parasitic inductance, diode behavior, dead time, and topology. A useful rough switching-loss estimate is:

Psw ≈ ½ × VDS × ID × (tr + tf) × fSW

This is a starting point, not a final prediction; use appropriate datasheet curves or models and validate the design when switching losses matter.

There is a common trade-off: a larger die can lower R_DS(on) but often increases gate charge and capacitance. Lower resistance is not automatically better if the driver cannot switch the device efficiently. Analog Devices discusses the resistance–gate-charge trade-off in its power-MOSFET selection note; ST identifies R_DS(on) × Q_G as one useful figure of merit on its MOSFET page.

The Miller plateau

During a drain-voltage transition, some gate current charges or discharges the gate-drain capacitance. The gate voltage therefore changes slowly for a period called the Miller plateau while drain voltage may change quickly. Miller charge is useful for assessing this interval, particularly in fast converters, half-bridges, motor drives, or layouts susceptible to switch-node coupling. A strong driver, short gate loop, and careful layout help control the transition and reduce unwanted turn-on.

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The body diode and reverse current

The intrinsic body diode can carry current when the MOSFET channel is off and the circuit drives current in the diode’s forward direction. In bridge circuits, synchronous converters, and motor drives, that conduction may add loss. When the diode is forced from conduction into reverse blocking, its stored charge can produce reverse-recovery current, voltage overshoot, electromagnetic interference, and extra heating.

Do not treat a body diode as an ideal substitute for an external fast diode. Check its forward voltage, current and thermal ratings, reverse-recovery time and charge, and the actual switching conditions. With the channel appropriately driven, many MOSFETs can also conduct in reverse through the channel; whether that helps depends on the circuit and timing. SiC MOSFET body-diode and reverse-conduction behavior differs from conventional silicon parts, so review the specific datasheet and gate-drive guidance. Toshiba provides MOSFET application material on reverse recovery and body-diode concerns.

How to read the important datasheet ratings

Voltage: Do not choose a MOSFET whose rating merely matches the nominal supply. Account for supply tolerance, transients, inductive kick, ringing, temperature, and layout. But do not choose an unnecessarily high voltage class without reason: higher ratings can bring greater on-resistance, gate charge, or cost. The appropriate margin depends on measured or well-characterized circuit peaks. Analog Devices illustrates the voltage-rating and resistance trade-off in its selection note.

Current: A datasheet current rating depends on assumptions such as case temperature, junction limit, package, mounting, PCB copper, and cooling. It is not a promise that a bare part on any board can carry that current. Also account for RMS, peak, startup, inrush, fault, and duty-cycle currents.

Gate limits and drive: Check maximum positive and negative V_GS. A gate clamp or careful drive and layout may be needed if ringing threatens the limit. “Logic-level” is not a universal guarantee: the decisive evidence is a guaranteed R_DS(on) at the actual controller voltage.

SOA, avalanche, and thermal: SOA is particularly important for linear operation, startup, current limiting, and fault pulses. Avalanche ratings apply only under stated conditions and do not automatically qualify repetitive avalanche in your design. A basic steady-state thermal estimate is TJ ≈ TA + PD × RθJA. With a heat sink, estimate from the relevant junction-to-case, interface, and sink-to-ambient thermal resistances. These are first-order checks; pulsed operation can require transient thermal impedance data. Package, board layout, Kelvin-source availability, mechanical fit, and creepage also matter.

Building a basic low-side switch

A common beginner circuit uses an N-channel enhancement MOSFET to switch a load connected to a positive supply:

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+V
 |
Load
 |
Drain
 N-channel MOSFET
Source
 |
Ground

MCU GPIO ── gate resistor ── Gate
                              |
                         pull-down resistor
                              |
                            Ground

1. Choose a MOSFET with on-resistance specified at the GPIO’s actual output voltage, such as 3.3 V or 5 V. A threshold number is not enough.
2. Connect the controller ground and source to a suitable common reference unless the control circuit is intentionally isolated.
3. Add a gate pull-down so the device stays off while the controller resets, is disconnected, or leaves the pin high impedance.
4. Use a gate resistor where needed to limit peak current, damp ringing, and control electromagnetic interference. Its value is a design choice, not a universal requirement.
5. For a motor, relay, solenoid, or other inductive load, provide an appropriate flyback or clamping path.
6. Check steady and startup current, PWM frequency, loss, package, and thermal conditions; keep the high-current loop compact.

A GPIO may fail to drive a large power MOSFET quickly enough, even when average gate-drive power looks small. Slow transitions can raise switching loss and heating, and high dv/dt can couple through Miller capacitance and cause false turn-on. Use a gate driver when gate charge, switching frequency, or circuit conditions require one.

High-side switches and bridge drives

Gate voltage is measured relative to the MOSFET’s source, not automatically relative to ground. In a high-side N-channel circuit, the source rises with the switch node; driving the gate to 10 V relative to ground may provide little or no useful gate-to-source voltage once the source also approaches 10 V.

• P-channel high-side switch: often has a simple drive arrangement for modest switching speeds and currents, with an on-resistance trade-off.
• N-channel with bootstrap driver: common in half-bridges and converters. The driver raises the high-side gate above its source. A bootstrap supply has operating constraints, including the need to recharge under appropriate switching conditions.
• Charge-pump or isolated driver: can support high-side operation where a bootstrap arrangement is unsuitable, including some static high-side and isolated applications.

In a half-bridge, simultaneous high-side and low-side conduction creates shoot-through current. Use a suitable gate driver, appropriate dead time, controlled gate transitions, and layout that limits common-source inductance and switch-node coupling. SiC devices may need particular attention to driver requirements and gate-voltage excursions; see ST’s SiC MOSFET documentation.

Worked screening example: 12 V load, 5 A, 3.3 V GPIO

Suppose a design must switch a 12 V load drawing 5 A continuously, with a 20 A startup pulse, using 20 kHz PWM and a 3.3 V GPIO in a 50 °C ambient. These figures are enough to screen candidates, not enough to declare a finished design or name a guaranteed part.

1. Set voltage needs: determine actual supply tolerance and measure or estimate drain-voltage overshoot, including startup and load transients. Select a voltage rating with margin over the real peak, not merely 12 V nominal.
2. Confirm drive: require a guaranteed R_DS(on) at 3.3 V or a lower gate voltage if the GPIO’s high level can sag. A device specified only at 10 V is not validated by a low threshold voltage.
3. Estimate conduction loss: as an illustration only, if the hot on-resistance were 20 mΩ and current were a continuous 5 A, then P ≈ 5² × 0.020 = 0.5 W. Actual PWM RMS current, duty cycle, temperature, and switching losses will change the result.
4. Check the pulse: a 20 A startup event must fit the device’s pulsed current and SOA conditions for its duration and starting temperature. The headline continuous current is not sufficient evidence.
5. Check switching: at 20 kHz, compare total and Miller charge with the GPIO or driver’s available source/sink current. If transitions are too slow or gate voltage is disturbed, use a driver and revisit layout.
6. Check thermal path: estimate the junction temperature at 50 °C ambient using hot conduction resistance and switching losses, then account for the actual PCB copper and cooling. If the load is inductive, design its clamp or flyback path as well.

This example deliberately does not nominate a component: without real transient voltage, pulse duration, duty cycle, thermal mounting, and guaranteed datasheet conditions, a specific part recommendation would be unjustified.

Where MOSFETs are used

• Digital logic: CMOS logic combines N-channel and P-channel devices. Stable logic states have low static power in many CMOS designs; dynamic power is largely associated with charging and discharging capacitances.
• Analog and RF: MOSFETs form common-source amplifiers, differential pairs, current mirrors, analog switches, and specialized RF circuits. Noise, capacitance, linearity, breakdown, and frequency behavior may matter more than minimum on-resistance.
• Power conversion: buck, boost, and buck-boost converters; synchronous rectifiers; bridges; motor controllers; inverters; and battery-management systems.
• Power-path control: reverse-polarity protection, ideal-diode circuits, hot-swap control, battery disconnects, and power multiplexing.

Silicon MOSFETs, SiC, and GaN

Silicon MOSFETs are the broad, general-purpose choice for many low- and medium-voltage switches and power converters. They are available across many packages and price points, but the right part still depends on voltage, resistance, charge, thermal performance, and topology.

Silicon-carbide MOSFETs are relevant to high-voltage, high-temperature, or high-performance power conversion such as EV inverters, solar inverters, industrial drives, and high-voltage supplies. They can offer useful switching and temperature characteristics in suitable designs, but usually cost more and may impose more demanding gate-drive and layout requirements. Their diode and reverse-conduction behavior also needs specific analysis. SiC is not an automatic drop-in upgrade for a silicon design.

Gallium-nitride (GaN) power transistors are commonly enhancement-mode HEMTs or related structures, not conventional silicon MOSFETs. They can switch very quickly with low charge in suitable voltage ranges, but require careful drive, layout, voltage margin, and protection. Call a device by its manufacturer’s terminology rather than assuming every GaN transistor behaves like a MOSFET.

When another switch may be a better fit

• BJT: may suit some analog or low-cost circuits, but it is current-driven and has different drive and switching behavior. A MOSFET’s insulated gate is often convenient for switching, though neither technology wins every use case.
• IGBT: can be attractive in some high-voltage, high-current applications. MOSFETs generally switch faster and avoid the IGBT’s minority-carrier tail, while the better choice depends on voltage, frequency, and conduction loss.
• Relay: offers galvanic isolation and very low off-state leakage for slow switching. MOSFETs are silent, compact, fast, and suitable for PWM, but do not inherently provide relay-style isolation.
• Integrated load switch or eFuse: adds features such as current limiting, thermal shutdown, controlled slew rate, short-circuit protection, reverse-current blocking, or diagnostics. A discrete MOSFET offers more freedom where current, voltage, cost, or optimized performance dominates.

Common MOSFET failures and troubleshooting

• Floating gate: noise can turn the part on unexpectedly. Fit a pull-up or pull-down that establishes the intended default state.
• Weak or inadequate drive: a GPIO may leave a power MOSFET switching slowly, causing heat or susceptibility to false turn-on. Check gate voltage at the device and consider a driver.
• Gate overstress: ringing can exceed the maximum positive or negative V_GS. Shorten loops, control ringing, and consider a suitable gate-source clamp.
• Inductive spike or drain ringing: a turn-off transient can exceed V_DSS. Add a suitable clamp or snubber and reduce parasitic inductance; do not assume avalanche capability makes repeated spikes harmless.
• Body-diode recovery: recovery current can create overshoot, EMI, loss, and bridge shoot-through. Verify diode behavior and switching sequence.
• Linear-mode failure: switching capability does not guarantee safe operation while the MOSFET is partly on. Check SOA at the relevant voltage, current, pulse duration, and temperature.
• Thermal or package failure: the die’s capability may exceed what leads, bond wires, solder, PCB copper, or cooling can support. Evaluate the actual assembly.
• Incorrect source reference: in a high-side or floating circuit, calculate V_GS as gate minus source, not gate minus ground.

A MOSFET’s positive on-resistance temperature coefficient often helps static current sharing between parallel devices, but it does not guarantee safe dynamic sharing or safe linear operation. Paralleled parts still need attention to gate layout, thermal coupling, and switching imbalance.

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Selection checklist

1. What is the maximum real drain-source voltage, including switching transients?
2. What are the RMS, peak, startup, fault, and pulsed currents?
3. Is the device a low-side switch, high-side switch, bridge element, or linear pass device?
4. What gate voltage is actually available at the MOSFET source reference?
5. Is R_DS(on) guaranteed at that voltage and at a relevant temperature?
6. What are conduction and switching losses at the intended frequency and duty cycle?
7. Can the driver supply and remove the required gate charge without excessive transitions or ringing?
8. Will reverse current flow, and is the body diode or channel conduction suitable?
9. Does SOA cover startup, current limiting, and fault pulses? Are avalanche assumptions justified?
10. Can the package and board dissipate the heat while meeting mechanical and insulation needs?
11. Are availability, lifecycle, qualification, and manufacturing requirements acceptable?

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