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The AMD Kria KV260 Vision AI Starter Kit uses a distinct embedded Vitis workflow: export your Vivado design as an .xsa, package it as a Vitis platform .xpfm, build a kernel and Linux host application, then deploy a device-tree overlay, acceleration binary and executable to the board’s existing Linux image. You normally do not rebuild the Starter Kit’s complete SD-card boot image for each accelerator.
This procedure follows AMD’s KV260-specific XD101 tutorial for Vitis 2025.1, released July 31, 2025. Menu names and paths can change in later releases, so verify them against the documentation shipped with your installed toolchain.
What the KV260 platform actually is
A Vitis platform is the reusable contract between Vivado hardware, Linux, XRT, memory, AXI control paths, interrupts, the Vitis linker and the host program. Vivado exports hardware information in an XSA; Vitis combines that information with software and runtime metadata to produce an XPFM platform description. See AMD’s platform-creation overview.
Do these 3 things before closing this tab:
1Clear out junk files and repair common Windows errors2Fix the driver behind crashes, sound loss and screen glitches3Repair Windows errors before they cause bigger problems| Artifact | Produced by | Role |
|---|---|---|
.xsa |
Vivado | Hardware design export |
.xpfm |
Vitis | Packaged acceleration platform |
pl.dtbo |
Vitis device-tree flow | Linux overlay describing programmable logic |
.xo |
Vitis kernel compiler | Kernel object before linking |
.xclbin |
Vitis linker | Kernel/system binary container |
.bin |
Deployment rename of the XCLBIN | Filename used by the documented KV260 application package |
shell.json |
Application package | Describes the XRT flat shell slot |
| Host executable | Vitis compiler | Linux program that opens XRT and launches the kernel |
Why KV260 is different from generic Vitis examples
The board contains a Kria K26 SOM with a Zynq UltraScale+ MPSoC, not a Versal AI Engine device. AMD’s product brief lists 256K system logic cells, 144 block-RAM blocks, 64 UltraRAM blocks, 1.2K DSP slices and 4 GB non-ECC DDR: KV260 product brief.
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In the Starter Kit flow, the supplied boot image is treated as fixed. Your application is loaded after Linux starts through xmutil, using a programmable-logic device-tree overlay and an acceleration binary under /lib/firmware/xilinx/<application>. This avoids rebuilding the FSBL, U-Boot, kernel and root filesystem for every kernel iteration. A custom PetaLinux system remains appropriate when you need kernel, rootfs, driver or boot-component changes.
Version and prerequisite checklist
| Item | Reference value |
|---|---|
| AMD document | XD101, Custom Kria SOM Platform Creation Example |
| Reference release | Vitis 2025.1 |
| Linux processor | psu_cortexa53 |
| Linux domain name | xrt |
| Common image family | xilinx-zynqmp-common-v2025.1 |
| Example sysroot | cortexa72-cortexa53-amd-linux |
Have a bootable KV260 SD card, Vivado and Vitis 2025.1 on a suitable Linux workstation, the matching AMD common image, a KV260-based Vivado design, Ethernet, SSH/SCP access, target-side XRT and enough disk space and RAM for synthesis and linking. The tutorial assumes the board already boots successfully: AMD’s KV260 example.
Step 1: create and export the Vivado hardware
Start from the KV260 preset or AMD reference design. Add the platform-required clocks, resets, AXI control and memory interfaces, and interrupt wiring; then validate the block design and export an XSA, for example:
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- Clocking: kernel and platform clocks must be defined and connected consistently.
- Reset: an incorrect reset topology can leave the kernel or platform unusable.
- AXI control: the processor needs a control path to the accelerator.
- Memory: kernel buffers must map to accessible DDR or another supported memory target.
- Interrupts: XRT depends on correct interrupt metadata and wiring.
Follow AMD’s hardware procedure at Create the Vivado Hardware Design and Generate XSA.
Step 2: package the XSA as a Vitis platform
- Initialize a workspace:
vitis -w . - In Vitis Unified IDE choose File > New Component > Platform.
- Name the platform, such as
kv260_custom, and selectkv260_hardware_platform.xsa. - In Advanced Options, leave SDT Source Repo, Board DTSI and User DTSI empty unless your design needs them. Enable DT ZOCL so the generated device tree contains the XRT ZOCL node.
- Set operating system to
Linux, processor topsu_cortexa53, and rename the Linux domain toxrt. - Select the matching common-image directory when software components are requested, then build the platform.
The resulting file is typically similar to WorkSpace/kv260_custom/export/kv260_custom/kv260_custom.xpfm. The same flow generates the PL device-tree data used to create pl.dtbo; it must come from the same hardware design as the XSA and XCLBIN. Details are in Create the Vitis Platform and Step 2: Create the Vitis Platform.
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Sysroot, common image and optional PetaLinux
For the standard Starter Kit flow, the common image is mainly valuable as a matching sysroot because the board already has its boot image. The example uses xilinx-zynqmp-common-v2025.1/sysroots/cortexa72-cortexa53-amd-linux to cross-compile the host.
If you need a custom kernel, root filesystem or device tree, use AMD’s optional BSP route. Enable packagegroup-petalinux-vitis-acceleration-essential and, when needed, packagegroup-petalinux-vitis-acceleration-dbg, then build:
petalinux-config -c rootfs
petalinux-build
petalinux-build --sdk
That route gives control over Linux and boot components but introduces longer builds and tighter version coupling. See AMD’s optional BSP procedure.
Configure the development environment
source <Vitis_install_path>/settings64.sh
source /opt/xilinx/xrt/setup.sh
export PLATFORM_REPO_PATHS=<path to platforms>
Vitis and XRT are used in different places: Vitis builds on the workstation, while XRT libraries, drivers and ZOCL support run on the KV260. A host linked against one sysroot should not be assumed compatible with an unrelated target image.
Validate the platform before building an application
platforminfo ./kv260_custom/export/kv260_custom/kv260_custom.xpfm
The reference output identifies platform kv260_custom, Vitis 2025.1, FPGA family zynquplus, device xck26, board xilinx.com:kv260_som:1.4, board part xck26-sfvc784-2LV-c, clocks near 100, 200 and 400 MHz, and a Linux Cortex-A53/XRT domain. If board, device, clocks, memory tags or runtime are wrong, fix the platform before debugging kernel code. See AMD’s platforminfo test.
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Build a first kernel and host program
- Open the Vitis Examples view and choose Simple Vector Addition.
- Select Create Application from Template and use a system name such as
vadd. - Select the
kv260_customplatform and set the sysroot toxilinx-zynqmp-common-v2025.1/sysroots/cortexa72-cortexa53-amd-linux. - Build the hardware target, binary container and host component.
Typical outputs are:
WorkSpace/vadd/build/hw/hw_link/binary_container_1.xclbin
WorkSpace/vadd_host/build/hw/vadd_host
The XCLBIN contains the linked system bitstream and kernel metadata. Unlike a generic Alveo deployment, this KV260 example does not put a new kernel image and root filesystem into a complete SD-card image.
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Package the KV260 application
Rename the generated XCLBIN for the documented Starter Kit deployment and create the application directory:
vadd/
├── pl.dtbo
├── binary_container_1.bin
└── shell.json
The example shell.json is:
{
"shell_type": "XRT_FLAT",
"num_slots": "1"
}
The overlay, binary and shell description must describe one coherent build set. Do not reuse a DTBO from another XSA or copy an XCLBIN built against a different platform.
Transfer files and load the design
scp pl.dtbo binary_container_1.bin shell.json vadd_host
petalinux@<SOM Starter Kit IP>:/home/petalinux
On the KV260:
sudo mkdir -p /lib/firmware/xilinx/vadd
cd /home/petalinux
cp pl.dtbo binary_container_1.bin shell.json
/lib/firmware/xilinx/vadd
sudo xmutil listapps
sudo xmutil unloadapp
sudo xmutil loadapp vadd
A successful load reports vadd: loaded to slot 0. listapps shows known applications, unloadapp releases an occupied slot, and loadapp applies the overlay and loads the acceleration binary. The exact deployment sequence is documented in AMD’s vector-addition test.
Run the host application
chmod +x ./vadd_host
./vadd_host binary_container_1.bin
The reference result is:
TEST PASSED
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Platform metadata is wrong
Recheck the XSA selected during platform creation, the KV260 board part, psu_cortexa53 processor and xrt domain. Do not substitute Versal examples that use different processor names or boot assumptions.
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xmutil loadapp fails
- Confirm all three package files are under
/lib/firmware/xilinx/vadd. - Regenerate
pl.dtbofrom the same XSA used for the platform and XCLBIN. - Run
sudo xmutil listapps, unload the existing application, then retry. - Check that the application name matches the directory name.
The host cannot find XRT
AMD’s example reports libxilinxopencl.so.2: cannot open shared object file when XRT is absent and suggests:
sudo dnf install xrt
That command is image-dependent. Check the package manager, repositories and XRT version supplied by your particular KV260 image before installing anything.
The executable runs but the ABI is incompatible
Rebuild the host with a sysroot matching the booted target image. Mixing arbitrary Vitis, common-image, PetaLinux and XRT releases can produce missing libraries or runtime incompatibilities.
The binary is still named .xclbin
The documented KV260 package uses binary_container_1.bin, and the host command must reference that deployed filename. The rename is a KV260 application convention, not a universal rule for every Vitis target.
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Prebuilt KV260 applications
Use AMD’s supplied applications when you only need a demonstration or vision-AI experiment and do not need custom programmable-logic hardware or kernels.
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Custom PetaLinux
Choose PetaLinux when you need additional drivers, kernel configuration, rootfs packages, device-tree changes or production boot integration. Expect more build time and maintenance.
ZCU104 or Versal platforms
A ZCU104 can be useful for generic Zynq UltraScale+ learning, while Versal boards suit AI Engine development. Their processor names, platform metadata, boot model and deployment steps are not interchangeable with the KV260 procedure.
Likewise, xmutil loading is runtime application loading through an overlay and binary; it should not be described as full Vivado Dynamic Function eXchange.
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Frequently Asked Questions
Do I need to generate a new KV260 SD-card image for every kernel?
Not for AMD’s standard Starter Kit application flow. Keep the supplied boot image and deploy the matching pl.dtbo, renamed binary, shell.json and host executable under /lib/firmware/xilinx/<app>.
Why is a device-tree overlay required?
The KV260 loads programmable-logic hardware after Linux boots. pl.dtbo describes that hardware to Linux and XRT, including devices and interrupts.
Can I use a Versal Vitis tutorial for KV260?
No. KV260 is a Zynq UltraScale+ MPSoC platform with a psu_cortexa53 domain; Versal examples use different processors, platform architecture and boot procedures.
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