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Intel did not launch a generally available product. On June 26, 2024, the company said it had demonstrated an optical compute interconnect (OCI) chiplet co-packaged with an Intel CPU at OFC 2024. Intel reported up to 4 Tbps of aggregate bidirectional bandwidth, but described the implementation as a prototype being developed with select customers.
The demonstration matters because co-packaged optical I/O could help future AI and HPC systems move data between CPUs, GPUs, memory resources and other accelerators with less electrical-I/O loss than long copper paths or conventional pluggable optical modules.
What Intel demonstrated
Intel’s OCI chiplet combines a silicon-photonics optical circuit with an electrical IC in a package alongside an Intel CPU. Intel says the silicon-photonics circuit includes on-chip lasers and optical amplifiers, allowing optical conversion to take place much closer to the processor than it does in a conventional system with remote pluggable transceivers.
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“Fully integrated” does not mean that the CPU performs optical computing or that an entire data-center network fits inside one chiplet. The optical technology handles data movement; electronic processors and controllers continue to perform computation and control.
Intel’s announcement calls the demonstration the industry’s first fully integrated, bidirectional optical compute interconnect chiplet of this type. That “first” claim should be understood as Intel’s characterization, not as an independently surveyed industry finding.
The headline specifications
| Specification | Intel-reported detail |
|---|---|
| Technology | Optical compute interconnect, or OCI, chiplet |
| Status | Prototype |
| Bandwidth | Up to 4 Tbps bidirectional |
| Channels | 64 channels at 32 Gbps per direction |
| Reach | Up to 100 meters of optical fiber |
| Energy efficiency | About 5 pJ/bit, compared with approximately 15 pJ/bit for the pluggable optics in Intel’s comparison |
| Optical multiplexing | Eight DWDM wavelengths per fiber, with 200 GHz spacing demonstrated |
| Fiber configuration | Eight fiber pairs |
| Interconnect compatibility | PCIe Gen5 |
Why “4 Tbps” needs qualification
The 4-Tbps figure is an aggregate bidirectional interface number, not 4 Tbps in one direction. Intel’s configuration used 64 channels at 32 Gbps:
64 × 32 Gbps = 2.048 Tbps in one direction.
Combining transmit and receive directions produces approximately 4.096 Tbps, which Intel rounds to 4 Tbps bidirectionally. Actual application-level payload throughput can be lower because of protocol overhead, encoding, implementation details and system architecture.
Why optical I/O is relevant to AI clusters
Modern AI systems connect large numbers of GPUs, CPUs, IPUs, memory pools and other accelerators. As systems scale, moving data between those components can become a constraint alongside compute capacity and memory bandwidth.
Short copper traces can be efficient and relatively simple, but their useful reach is limited. Intel characterizes conventional electrical I/O as reaching roughly one meter or less in the relevant high-bandwidth context. Longer electrical paths require increasingly difficult signal-integrity measures, while conventional optical links typically place conversion hardware in pluggable modules away from the processor.
Co-packaged optical I/O moves the optical interface closer to the compute die. That can shorten the high-speed electrical path between the processor and optical conversion, potentially reducing losses and improving bandwidth density. Fiber can then carry the signal over distances that would be impractical for package- or board-level copper.
The expected benefit is not that optical I/O makes the CPU or GPU calculate faster by itself. Its value is architectural: it may make it easier to connect more computing resources, pool memory, or disaggregate components without spending as much power and package area on long electrical links.
Lasers, wavelengths and fiber
Intel said the demonstration used eight dense wavelength-division multiplexing (DWDM) wavelengths on a single fiber, with eight fiber pairs in the reported configuration. DWDM assigns separate optical wavelengths to multiple data channels, allowing them to share fiber rather than requiring one fiber for every electrical lane.
Intel also described the chiplet as including on-chip lasers and optical amplifiers. Integrating these functions with the optical circuit can reduce the distance between the electrical interface and the optical transmitter or receiver, although it also makes package design, thermal management and manufacturing more complex.
What the 5-pJ/bit claim means
Intel reported approximately 5 pJ/bit for the co-packaged solution, compared with roughly 15 pJ/bit for the pluggable optical transceiver modules used as its comparison point. On those figures, the co-packaged approach uses about one-third as much energy per transferred bit, or roughly two-thirds less.
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This is an Intel-reported interconnect comparison, not an independently validated data-center benchmark. It is also not total system power and not energy per AI operation. The final result would depend on what is included in the measurement, including drivers, lasers, receivers, retimers, package losses, cooling and host-interface overhead. The figures therefore should not be converted directly into a guaranteed percentage reduction in a complete AI cluster’s electricity use.
Reach is constrained by latency, not only signal quality
Intel specified up to 100 meters of fiber reach but cautioned that practical applications could be limited to tens of meters because of time-of-flight latency. A signal may remain optically viable over 100 meters while the architecture using it cannot tolerate the associated delay.
The useful distance depends on the protocol, synchronization requirements, topology and workload. A link between nearby accelerators may have different requirements from one connecting disaggregated memory or resources across a rack. The 100-meter number should therefore be treated as a stated maximum capability, not a universal deployment recommendation.
Potential system architectures
Intel identified several possible uses for OCI:
- Larger CPU and GPU clusters.
- Coherent memory expansion.
- Memory pooling and resource disaggregation.
- Connections among CPUs, GPUs, IPUs and other SoCs.
- xPU systems in which compute resources are assembled more flexibly.
These are potential architectures, not results demonstrated by a production AI system. Intel did not announce a public cloud deployment, a benchmarked memory-pooling platform or a measured training or inference improvement.
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Intel described the demonstrated implementation as compatible with PCIe Gen5. That does not make OCI a new PCIe generation. It is better understood as an optical implementation of an interconnect path compatible with PCIe Gen5 signaling or system requirements, as Intel described it.
Nor does PCIe Gen5 compatibility establish compatibility with every accelerator fabric, CXL deployment, Ethernet system or proprietary scale-up protocol. A commercial implementation would still require appropriate package design, firmware, protocol support, validation and system integration.
What Intel has not announced
The June 2024 announcement did not provide a product SKU, price, ordering page, general availability date or public list of production deployments. Intel said it was working with select customers to co-package OCI with their SoCs, but the demonstrated chiplet remained a prototype.
That means readers cannot buy an OCI chiplet, install one in an existing server or add it to a current AI cluster as an upgrade. Intel’s broader silicon-photonics products are relevant background, but they are not equivalent to this demonstrated co-packaged OCI implementation.
Deployment challenges
Co-packaged optics offers potential power and bandwidth advantages, but it introduces important operational questions:
- Serviceability: A failed optical interface may be less easily replaced than a pluggable transceiver.
- Packaging yield: Optical and electronic die must be integrated and qualified together.
- Thermals: Lasers, amplifiers, drivers and high-performance compute silicon must coexist within tight thermal limits.
- Fiber management: Systems need appropriate connectors, routing, bend-radius control and rack-level cabling.
- Interoperability: A customer may need a matched Intel and SoC ecosystem rather than universally interchangeable modules.
- Latency: Longer fiber links may be signal-capable but unsuitable for latency-sensitive memory or scale-up architectures.
- Economics: Lower energy per bit must offset the cost and complexity of advanced packaging, optics and qualification.
OCI compared with other approaches
Electrical package and board traces remain attractive for short connections because they are comparatively simple and serviceable. Pluggable optical transceivers offer mature data-center deployment models and field replacement, but they add module-level conversion and power overhead.
Other co-packaged-optics designs pursue a similar goal with different optical-engine, packaging and serviceability choices. Proprietary accelerator fabrics may deliver tightly optimized scale-up performance but can reduce cross-vendor interoperability. CXL is relevant to memory expansion and pooling, but it is a protocol and system architecture; optical I/O is a possible physical transport layer, not a replacement for CXL or a complete AI networking stack.
Intel also said it was developing 200G-per-lane photonic integrated circuits for 800-Gbps and 1.6-Tbps applications. Those figures describe development or roadmap work, not an available OCI product specification.
Bottom line
Intel’s OCI demonstration is a meaningful proof point for placing optical connectivity directly beside compute silicon. The reported 4-Tbps bidirectional interface, 5-pJ/bit comparison and fiber reach illustrate why co-packaged optics is being considered for future AI and HPC systems.
But the June 26, 2024 announcement was a prototype demonstration at OFC 2024—not a commercial launch. There is no disclosed price, general availability date, public production deployment or complete AI workload benchmark. OCI is best viewed as an enabling technology that could help solve future bandwidth and interconnect-power problems, provided Intel and its customers overcome packaging, latency, serviceability, interoperability and manufacturing challenges.
Intel investor-relations release · Intel technical-context post
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