Quick wins for a faster PC:
Clear out junk files and repair common Windows errorsFree Scan →Scan for outdated or missing drivers - takes under a minuteDriver Scan →Some links on this page are affiliate links: if you buy through them we may earn a commission, at no extra cost to you.
Yes, an ADC-to-DAC loopback is possible with an ADRV9009-W/PCBZ and AMD/Xilinx ZCU102, but “digital loopback” can describe different tests. The ADRV9009’s internal framer/deframer loopback checks a digital path while bypassing the converters. A genuine ADC-to-DAC loopback must carry received ADC samples through the FPGA fabric, DMA, or both, and then return them to the transmitter.
For the supported reference platform, connect the ADRV9009-W/PCBZ to the ZCU102’s FMC HPC1 connector and start from ADI’s adrv9009_zcu102 HDL project. Validate the stock design first; only then add custom RX-to-TX processing.
Choose the loopback you actually need
Before changing HDL or software, identify which signal path must be tested. These modes are not interchangeable:
Outdated Drivers Are Slowing You Down
One free scan finds every outdated or missing driver and matches the right update for your exact hardware.Free scan · exact hardware matchPC Slower Than It Used to Be?
A free scan shows the junk files, broken settings and background clutter dragging Windows down - then fixes them in one click.Free scan · Windows 10 & 11| Mode | Signal path | Exercises ADC and DAC? | Best use |
|---|---|---|---|
| Framer/deframer loopback | TX digital data back into the digital RX path | No | JESD204B and digital-link validation |
| FPGA fabric loopback | RX JESD/ADC samples through FPGA logic into TX JESD/DAC | Yes | Real-time FPGA DSP and deterministic low-latency testing |
| DMA loopback | RX samples to DDR, software or DMA movement, then TX | Yes | Finite-buffer and software-controlled tests |
| External RF loopback | TX RF output through attenuation and cable into RX or ORx | Yes, including the RF path | End-to-end RF and analog verification |
| Calibration feedback | Transmitter feedback through an observation receiver | Not equivalent to a user RX-to-TX loopback | TX calibration, feedback and DPD-related functions |
The distinction matters most for the internal framer loopback. ADI’s ADRV9009 driver documentation describes this as injecting transmit data into the digital receive path while bypassing the analog and converter sections. It can prove that the digital link is functioning, but it cannot prove that the ADC, DAC, RF gain settings, clocks or external RF routing work.
#1 Best Overall
- Transmission: Significantly enhanced transmission rates for faster, more convenient operation
- Processing: Robust onboard storage and processing capabilities support integration with dedicated sensors and devices, with minimal operational load
- Reliability: Dependable performance scalable across diverse application scenarios
- Materials: Manufactured using eco-friendly production techniques and materials, with functional, voltage, and current testing completed prior to packaging
- Applications: Ideal for home, building, and industrial automation sectors
Required hardware and software
- ADRV9009-W/PCBZ radio card.
- AMD/Xilinx ZCU102 evaluation kit.
- Connection from the radio card to FMC HPC1.
- Board power, UART and, for Linux workflows, Ethernet.
- Optional JTAG access for no-OS programming and debugging.
- A compatible Vivado/Vitis release and the ADI HDL repository.
- Either a matching Linux image and device tree or a matching ADI no-OS project.
- A valid ADRV9009 RF profile and the appropriate Talise evaluation or configuration software resources.
ADI documents the ZCU102 as a supported carrier for the ADRV9009-W/PCBZ in its quick-start material. The ADRV9009 itself provides dual transmitters, dual receivers and observation-receiver functionality, with a documented tuning range of 75 MHz to 6 GHz and a JESD204B digital interface. See the ADRV9009 product page for device-level capabilities.
Lock the versions before building
Do not combine an HDL bitstream, XSA, device tree, no-OS application and RF profile from unrelated releases without checking compatibility. Record at least:
- HDL repository commit or release.
- no-OS repository commit or release.
- Vivado and Vitis versions.
- Linux image and device-tree revision, if applicable.
- RF profile or Talise Evaluation Software version.
- ZCU102 board revision.
- ADRV9009-W/PCBZ revision.
The current ADI no-OS example documentation shows a Vitis 2025.1 environment, but that is a version-specific example rather than a permanent requirement. Treat the commands and project structure as release-dependent.
Start with the stock ADI HDL design
Use ADI’s adrv9009_zcu102 reference project as the baseline. From a checked-out HDL repository, the documented default build is:
cd hdl/projects/adrv9009/zcu102
makeThe project also supports parameterized JESD configurations. For example:
make TX_JESD_M=4 TX_JESD_L=4
RX_JESD_M=4 RX_JESD_L=2
RX_OS_JESD_M=2 RX_OS_JESD_L=2Build and boot this unchanged design before inserting a loopback. Confirm that the board initializes, the RF profile loads, the JESD links establish and the standard capture or transmit tests behave as expected. A modified design is much harder to debug if the original baseline was never proven.
Reference datapath and documented rates
The reference design uses separate JESD204B paths for transmit, receive and observation-receiver data. One documented example uses the following values:
| Path | JESD parameters | Sample rate | Example lane rate |
|---|---|---|---|
| RX | L=2, M=4, F=4, S=1, NP=16, N=16 | 245.76 MSPS | Approximately 9.83 Gbps |
| ORx | L=2, M=2, F=2, S=1, NP=16, N=16 | 491.52 MSPS | Reference-dependent |
| TX | L=4, M=4, F=4, S=1, NP=16, N=16 | 491.52 MSPS | Approximately 9.83 Gbps |
The design documentation also shows a 245.76 MHz device/reference-clock example, a 64-bit receive interface and a 128-bit transmit interface at the stated configuration. These are documented reference values, not universal ADRV9009 requirements. A different profile or parameter set changes the rates, widths and possibly clock relationships.
Rank #2
- Transmission: Significantly enhanced transmission rates for faster, more convenient operation
- Processing: Robust onboard storage and processing capabilities support integration with dedicated sensors and devices, with minimal operational load
- Reliability: Dependable performance scalable across diverse application scenarios
- Materials: Manufactured using eco-friendly production techniques and materials, with functional, voltage, and current testing completed prior to packaging
- Applications: Ideal for home, building, and industrial automation sectors
The conceptual converter loopback is:
ADRV9009 RX
↓
JESD204B RX
↓
ADI receive/converter path
↓
RX sample unpacking or receive DMA
↓
Custom FPGA processing or FIFO
↓
TX sample repacking
↓
TX DMA or AXI-stream source
↓
JESD204B TX
↓
ADRV9009 DAC and transmitterThe HDL documentation describes ADC data being sent toward DDR through DMA and DAC data being supplied by an internal generator or external DDR through DMA. It does not mean that an ADC stream is automatically wired directly to the DAC.
Build a genuine FPGA RX-to-TX loopback
A fabric loopback is the right approach for continuous, low-latency processing. Insert custom logic at a stable, documented interface in the ADI datapath rather than simply connecting low-level buses whose packing and handshake contracts are not understood.
1. Unpack and label the RX samples
Determine the exact word layout for the selected HDL revision: I and Q order, signedness, sample width, channel interleaving and lane-to-channel relationship. Treat channel labels as explicit metadata in your design. Do not assume that a visually plausible waveform means the mapping is correct.
What’s actually slowing this PC down?
Pick the symptom - the matching free tool is one click away.
2. Add the processing stage
Start with a transparent pass-through or a known gain. Then add a distinctive test pattern, gain, clipping, filter or other DSP function. Keep the first implementation simple enough that every output word can be predicted.
3. Cross the clock domains deliberately
The reference configuration has different RX and TX interface widths and the ADI support discussion identifies separate RX and TX clock domains. Use an asynchronous or dual-clock FIFO unless your specific configuration proves that both interfaces share a suitable clock and timing relationship.
The FIFO should provide elasticity for clock differences and backpressure. Monitor occupancy, overflow and underflow. A loopback that works only while the FIFO happens to start at a favorable fill level is not a reliable design.
4. Repack for the TX path
The TX interface is wider in the documented reference configuration, and the JESD lane arrangement differs from RX. Repack the processed I/Q samples into the exact TX format. Account for:
The Tool Desk
Outbyte PC Repair FREERepair Windows errors before they cause bigger problemsFix Now →Outbyte Driver Updater FREEScan for outdated or missing drivers - takes under a minuteDriver Scan →- Different bus widths.
- Different lane counts.
- Channel ordering.
- I/Q ordering and sign extension.
- Sample-rate differences or deliberate rate conversion.
- AXI-stream
valid,readyandlastbehavior.
5. Select and verify the TX source
The TX path may select an internal DDS or pattern generator, a DAC buffer, DMA data or another source depending on the project revision. If the custom stream is not selected, the loopback logic can be correct while the DAC continues to receive a different source. The ADI EngineerZone discussion associated with this reference design specifically highlights DAC buffer output selection, DMA descriptors and TX-channel controls.
Rank #3
- 1. Adding a gigabit Ethernet port can support some functions of ZEDBOARD+FMCOMMS2-3. The corresponding firmware is also provided in the documentation, but it does not support USB ports;
- 2. Add a JTAG port, which supports power supply, FPGA debugging, and serial port functions, making it convenient for some friends to develop bare metal drivers. In the factory firmware, this JTAG port is used as the boot information output interface, and also for configuring network port IP addresses and other functions.
- 3. Replace the main control chip, the original Pluto main control chip is XC7Z010-CLG225, changed to XC7Z020-CLG400; Increase DDR capacity to 1GB;
- 4. Introduce dual transmitter and dual receiver on the RF interface, and crack it into 9361 using the original firmware; Introduce several GPIO for users to expand their functions;
- 5. Strict simulation and impedance control of the RF part, adding PA to increase output power
6. Instrument the design
Add an ILA or equivalent FPGA debug instrumentation at the RX tap, FIFO input and output, and TX input. Capture:
- RX sample words and channel identifiers.
- FIFO levels and error flags.
- TX
valid/readyhandshaking. - Underflow and overflow events.
- Pattern alignment and expected latency.
Validate one channel first. Only after its I/Q ordering and timing are correct should all channels and the observation path be enabled.
A quick TX-path loopback control
An ADI EngineerZone support response from 2019 documented a DAC-channel control in which writing 0x08 to REG_CHAN_CNTRL_7 for each channel selected “loopback data.” The response refers to the axi_adrv9009_tx_channel.v implementation and the DAC channel register map.
Use this only as a version-sensitive TX-path test. Verify the register offset, field definition and behavior against the HDL revision you are building. It is not proof of a complete ADC-to-DAC path and should not replace explicit RX-to-TX fabric logic when custom processing is required.
Reference: ADI EngineerZone loopback discussion.
DMA and no-OS: the simpler software loopback
For a software-controlled test, use this flow:
RX ADC samples → DMA → DDR buffer → software copy or processing → TX DMA → DACADI’s current no-OS documentation lists demo, dma_example, iio, adrv9008-1 and adrv9008-2 variants. The dma_example is the most relevant starting point for exercising ADC and DAC paths through DMA. It is not automatically a continuous, zero-copy fabric loopback.
For a ZCU102 hardware design, the documented build pattern is:
source ~/.xilinx/2025.1/Vitis/settings64.sh
cd no-OS
python tools/scripts/no_os_build.py build
--project adrv9009
--variant demo
--board zcu102
--hardware /path/to/adrv9009_zcu102/system_top.xsaFor the DMA test:
python tools/scripts/no_os_build.py build
--project adrv9009
--variant dma_example
--board zcu102
--hardware /path/to/adrv9009_zcu102/system_top.xsaThe IIO example is useful for interactive capture and control:
python tools/scripts/no_os_build.py build
--project adrv9009
--variant iio
--board zcu102
--hardware /path/to/adrv9009_zcu102/system_top.xsaADI also documents JTAG/OpenOCD options for compatible setups:
Rank #4
- Arty A7 comes in two FPGA variants: Arty A7-35T features Xilinx XC7A35TICSG324-1L. Arty A7-100T features the larger Xilinx XC7A100TCSG324-1.
- Internal clock speeds exceeding 450MHz, On-chip analog-to-digital converter (XADC), Programmable over JTAG and Quad-SPI Flash
- 256MB DDR3L with a 16-bit bus @ 667MHz, 16MB Quad-SPI Flash, USB-JTAG Programming circuitry, Powered from USB or any 7V-15V source
- 10/100 Mbps Ethernet, USB-UART Bridge
- 4 Switches, 4 Buttons, 1 Reset Button, 4 LEDs, 4 RGB LEDs, 4 Pmod connectors, shield connector
python tools/scripts/no_os_build.py build
--project adrv9009
--variant demo
--board zcu102
--hardware /path/to/adrv9009_zcu102/system_top.xsa
--probe openocd
--flashThese commands are tied to the documented no-OS release and toolchain. Check the current ADI no-OS project documentation before using them with another release.
DMA trade-offs
- Advantages: easier capture, easier software instrumentation, straightforward finite-buffer testing and less custom HDL.
- Disadvantages: memory latency, CPU or DMA scheduling, finite-buffer behavior, possible underruns and overruns, and less deterministic latency than a carefully designed streaming path.
Linux and IIO workflow
With Linux, use a matching image and device tree, then expose the transceiver and converter paths through ADI’s IIO infrastructure. IIO-Oscilloscope can assist with configuration and streaming, and ADI lists GNU Radio compatibility as part of the prototyping ecosystem.
- Boot the matching Linux image and device tree.
- Confirm that the ADRV9009 driver probes successfully.
- Check JESD204B link status.
- Load or select a valid RF profile.
- Enable the required RX, TX or ORx channels.
- Configure sample rate, bandwidth, LO and attenuation.
- Generate a known TX waveform or pattern.
- Capture RX or ORx data.
- Verify sample ordering, scaling and channel mapping.
- Move captured data into the TX buffer, or use the custom fabric loopback for continuous streaming.
Attribute names and debugfs paths vary by driver revision. Older ADI documentation shows controls such as:
Do these 3 things before closing this tab:
1Scan for outdated or missing drivers - takes under a minute2Clear out junk files and repair common Windows errors3Fix the driver behind crashes, sound loss and screen glitchesecho 1 > bist_framer_a_loopbackThat setting refers to internal framer loopback and therefore does not validate the ADC or DAC. Use the driver documentation corresponding to the exact Linux release rather than copying an older sysfs path blindly.
JESD204B lane mapping and sample integrity
The ADI design uses JESD204B 8B/10B; its documentation explicitly distinguishes this from JESD204C. The documented physical-to-FPGA lane mappings are:
ADC/RX
| ADC physical lane | FPGA logical lane |
|---|---|
| 0 | 0 |
| 1 | 1 |
ADC observation path
| ADC observation physical lane | FPGA logical lane |
|---|---|
| 0 | 2 |
| 1 | 3 |
DAC/TX
| DAC physical lane | FPGA logical lane |
|---|---|
| 0 | 3 |
| 1 | 2 |
| 2 | 0 |
| 3 | 1 |
Incorrect lane or channel mapping can produce data that looks valid but has swapped channels, corrupted I/Q pairs or an unexpected permutation. Use a different constant, ramp or PRBS-like pattern per channel and compare it at the RX and TX boundaries.
Independent reader supportYour contribution helps us test, update, and keep practical guides available for everyone.External RF loopback: test it last
An RF cable loopback exercises the transmitter output, analog routing, receiver or observation receiver, gain settings and ADC. It is different from a fabric loopback and should be attempted only after the digital path is understood.
Free tools Windows power users keep installed
One-click scans. No signup required.
Use an appropriate RF cable, connectors and attenuation. Do not assume one attenuator value is safe: the required attenuation depends on TX output power, frequency, board loss, RX or ORx attenuation, bandwidth and waveform crest factor. The ADRV9009 hardware reference manual discusses observation-receiver limits and gives an approximately −13 dBm full-scale observation-receiver input example at 0 dB attenuation for a single-tone input. Treat that as a documented example, not a universal safe level.
Best Value
- The best way to get started with FPGAs: Using a simple board with projects that build on eachother, now anyone can get started with FPGA development!
- Fun peripherals available: With 4 LEDs, 4 push-buttons, 7-segment display, USB connector, a VGA connector, and a PMOD (for expansion) you can have dozens of fun projects available to you out of the box!
- Works with Verilog and VHDL: No matter which programming language you want to get started with, the Go Board will work for you!
- No extra device required: Simply plug the Go Board into a USB port and go! Getting started with FPGAs has never been easier.
- Works with all operating systems: Windows, Mac, Linux
Begin with substantial attenuation, configure conservative TX and RX/ORx levels, and increase the signal only while monitoring with suitable RF equipment. A saturated observation receiver can make a correctly functioning digital loopback appear broken.
What success looks like
A useful acceptance checklist is:
- JESD links establish and remain stable.
- A known TX waveform appears at the intended RX or ORx capture point.
- A ramp or distinctive per-channel pattern survives the FPGA loopback without word or channel permutation.
- I/Q ordering and sign extension are correct.
- No FIFO underflow or overflow occurs.
- Measured latency and gain match the design expectation.
- DMA transfers complete without descriptor starvation.
- RF loopback remains below ADC or ORx full-scale.
- The result repeats after reboot and reinitialization.
Troubleshooting guide
JESD link does not establish
Check the FMC HPC1 connection, board identity, reference clock and SYSREF configuration, RF profile, lane rate, lane count, PLL settings and compatibility between the HDL, XSA, software and image. Return to the stock ADI bitstream, build the documented default project and verify the link before adding custom logic.
TX output is silent
Check that the TX channel is enabled, the intended source is selected, DAC buffer output is configured when required, DMA descriptors complete, AXI-stream valid/ready activity exists and no FIFO underflow is asserted. Also check TX attenuation, RF profile, the physical connector and the selected TX channel.
RX samples are scrambled
Check I/Q order, lane mapping, channel interleaving, sample width, signedness, sign extension and whether the data came from RX or ORx. Inject a unique ramp or constant into each channel and validate one channel at a time.
The loopback drops or repeats samples
Look for RX/TX clock-domain mismatches, insufficient FIFO depth, unhandled backpressure, unequal sample rates, DMA burst or descriptor starvation, incorrect last handling and TX underruns. Monitor FIFO occupancy and stream handshakes with an ILA.
RF loopback saturates
Increase attenuation, reduce TX output level, review RX/ORx gain and attenuation, account for waveform crest factor and confirm that the cable is connected to the intended input. Use RF test equipment to verify the level rather than relying only on software settings.
Internal loopback works but RF loopback fails
This is not contradictory. Internal framer loopback bypasses the converters and analog signal chain. A successful result proves only the relevant digital path; it does not validate the ADC, DAC, RF routing, gain, calibration or external cabling.
Recommended Free Tools
Linux device is missing
Check that the bitstream, device tree and kernel driver belong to the same design revision. Confirm boot logs, clocks, resets, SPI control and JESD status before debugging IIO channel configuration.
The no-OS build fails
Check the Vitis version, board argument, project variant and XSA path. The hardware file must correspond to the HDL build, and the documented commands may change between no-OS releases.
Quick Recap
Which path should you choose?
| Requirement | Recommended path |
|---|---|
| Verify JESD connectivity | Internal framer/deframer loopback |
| Verify ADC and DAC operation | Known TX waveform plus RX capture |
| Run real-time FPGA DSP | Fabric RX-to-TX loopback with explicit clocking and FIFO design |
| Prototype an algorithm quickly | DMA/DDR software loopback |
| Verify analog and RF behavior | External RF loopback with controlled attenuation |
| Test transmitter feedback | Observation-receiver calibration path |
| Minimize custom HDL | DMA loopback or a compatible existing TX source control |
| Minimize latency | Streaming fabric loopback |
| Use interactive host tools | Linux/IIO and IIO-Oscilloscope |
Recommended implementation order
- Build and boot the stock
adrv9009_zcu102design. - Confirm JESD204B links and RF initialization.
- Run an internal digital test only when the goal is link validation.
- Prove a known TX waveform and capture it through RX or ORx.
- Capture and document the RX word format and channel ordering.
- Insert a transparent FPGA pass-through with a clock-domain FIFO.
- Add a known gain or test pattern before adding complex DSP.
- Configure and verify the selected TX source, DMA descriptors and buffer behavior.
- Use ILA to verify data, handshaking, latency and FIFO health.
- Only then connect an attenuated RF cable for end-to-end testing.
Useful primary references
- ADI ADRV9009 HDL reference design
- ADI no-OS ADRV9009 project
- ADI ADRV9009 Linux driver documentation
- ADI EngineerZone loopback discussion
- ADRV9009 hardware reference manual, UG-1295
- ADI HDL source repository
- ADI no-OS source repository
Product prices and availability are accurate as of the date/time indicated and are subject to change. Any price and availability information displayed on Amazon at the time of purchase will apply.
